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path: root/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2023-10-31[RISCV][NFC] Simplify vector register decoding methods (#70423)flyingcat1-20/+6
2023-10-20[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)Brandon Wu1-0/+6
2023-08-19[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extens...Jim Lin1-1/+1
2023-07-30[RISCV] Rename XTHead DecoderNamespaces to match their extension names includ...Craig Topper1-11/+11
2023-07-30[RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV e...Craig Topper1-1/+1
2023-07-28 [RISCV] Add support for XCVbi extension in CV32E40Pmelonedo1-0/+2
2023-07-28Revert "[RISCV] Add support for XCVbi extension in CV32E40P"melonedo1-2/+0
2023-07-28[RISCV] Add support for XCVbi extension in CV32E40Pmelonedo1-0/+2
2023-07-28[RISCV] Add support for XCVsimd extension in CV32E40Pmelonedo1-0/+2
2023-07-28[RISCV] Add support for XCValu extension in CV32E40PQihan Cai1-0/+2
2023-06-26[RISCV] Add support for custom instructions for Sifive S76.Garvit Gupta1-0/+2
2023-06-21[RISCV] Add support for XCVmac extension in CV32E40PQihan Cai1-0/+2
2023-06-19[RISCV] Add support for XCVbitmanip extension in CV32E40Pmelonedo1-0/+3
2023-05-25[RISCV][NFC] Simplify decoding code of disassemblerwangpc1-146/+72
2023-05-16[RISCV] Rework how implied SP operands work in the disassembler. NFCCraig Topper1-22/+20
2023-05-08[RISCV] Add MC support of RISCV zcmp ExtensionWuXinlong1-0/+42
2023-05-05[RISCV] Add DecoderNamespace to Zcmt instructions.Craig Topper1-0/+8
2023-05-04[RISCV] Directly create MCOperands from addImplySP in Disassembler. NFCCraig Topper1-7/+6
2023-04-09[RISCV] Support assembler and dis-assembler for VCIX extension.Nelson Chu1-0/+7
2023-03-27[RISCV] Replace RISCV -> RISC-V in comments. NFCCraig Topper1-1/+1
2023-03-23[RISCV][MC] Add support for RV64EJob Noorman1-2/+2
2023-02-24[RISCV] Add vendor-defined XTheadCondMov (conditional move) extensionPhilipp Tomsich1-0/+7
2023-02-24[RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) exten...Manolis Tsamis1-0/+7
2023-02-24[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extensionManolis Tsamis1-0/+7
2023-02-22[RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extensionManolis Tsamis1-0/+7
2023-02-22[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extensionManolis Tsamis1-0/+7
2023-02-21[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extensionManolis Tsamis1-0/+37
2023-02-17[RISCV] Use MCSubtargetInfo::hasFeature where possible. NFCCraig Topper1-13/+11
2023-02-17Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) ...Philipp Tomsich1-37/+0
2023-02-17[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extensionManolis Tsamis1-0/+37
2023-02-14[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extensionManolis Tsamis1-0/+7
2023-02-13[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extensionPhilipp Tomsich1-0/+7
2023-02-13[RISCV] Add vendor-defined XTHeadBs (single-bit) extensionPhilipp Tomsich1-0/+7
2023-02-08Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension"Philipp Tomsich1-7/+0
2023-02-08Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension"Philipp Tomsich1-7/+0
2023-02-08[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extensionPhilipp Tomsich1-0/+7
2023-02-08[RISCV] Add vendor-defined XTHeadBs (single-bit) extensionPhilipp Tomsich1-0/+7
2023-02-08[RISCV] Add vendor-defined XTHeadBa (address-generation) extensionPhilipp Tomsich1-0/+7
2023-02-06[RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFCCraig Topper1-36/+26
2023-02-06[RISCV] Remove DecoderMethod from C_NOP_HINT. NFCCraig Topper1-15/+0
2023-02-06[RISCV][NFC] Update debug message for XTHeadVdotPhilipp Tomsich1-1/+1
2023-02-05[RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisass...Craig Topper1-41/+41
2023-02-05[RISCV] Simplify some code in RISCVDisassembler. NFCCraig Topper1-2/+2
2023-02-05[RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_...Craig Topper1-0/+16
2022-12-26[RISCV] Implement assembler support for XTHeadVdotJojo R1-0/+9
2022-11-14[RISCV] Implement assembler support for XVentanaCondOpsPhilip Reames1-0/+10
2022-05-15Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`Sheng1-1/+1
2022-03-25[Disassember][NFCI] Use strong type for instruction decoderMaksim Panchenko1-40/+46
2022-03-02[RISCV] add the MC layer support of Zfinx extensionShao-Ce SUN1-0/+32
2022-02-24Revert "[RISCV] add the MC layer support of Zfinx extension"Nikita Popov1-32/+0
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