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| author | Manolis Tsamis <manolis.tsamis@vrull.eu> | 2023-02-22 10:58:50 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-22 11:15:40 +0100 |
| commit | 16a6cf6a99c247375f2f95a922d59da81de81a2c (patch) | |
| tree | a80b4da0425c6d021d79180160529e970acd65e4 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 15f9cf164c00490484a06032182612474f723fbc (diff) | |
| download | llvm-16a6cf6a99c247375f2f95a922d59da81de81a2c.zip llvm-16a6cf6a99c247375f2f95a922d59da81de81a2c.tar.gz llvm-16a6cf6a99c247375f2f95a922d59da81de81a2c.tar.bz2 | |
[RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd
Depends on D144496
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144501
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index d7c7fcc..e278edc 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -541,6 +541,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.hasFeature(RISCV::FeatureVendorXTHeadSync)) { + LLVM_DEBUG(dbgs() << "Trying XTHeadSync custom opcode table:\n"); + Result = decodeInstruction(DecoderTableTHeadSync32, MI, Insn, Address, + this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) { LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n"); Result = |