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| author | Manolis Tsamis <manolis.tsamis@vrull.eu> | 2023-02-14 19:43:00 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-14 20:25:47 +0100 |
| commit | d4012bc43f9a752d77f464286d91f72f4c6970ee (patch) | |
| tree | 01ea11c7f9b99d9c570c2d15d2a8926b2d17f8a2 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 179db7efe567ed76e36b6c4d69605b426d8f70ca (diff) | |
| download | llvm-d4012bc43f9a752d77f464286d91f72f4c6970ee.zip llvm-d4012bc43f9a752d77f464286d91f72f4c6970ee.tar.gz llvm-d4012bc43f9a752d77f464286d91f72f4c6970ee.tar.bz2 | |
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154
Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143847
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 647607a66..b379976 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -492,6 +492,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadMac]) { + LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n"); + Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address, + this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) { LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n"); Result = |