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| author | Craig Topper <craig.topper@sifive.com> | 2023-02-05 22:42:57 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-02-05 23:44:12 -0800 |
| commit | d2fd0d3cbc2e3fbd813189e0342fa78d3a0e7057 (patch) | |
| tree | a4c857c95e26db182fbb4401f92bdd9f3e73d085 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | be3f4591aff07204bdc0f6eda0ea70de44c08af6 (diff) | |
| download | llvm-d2fd0d3cbc2e3fbd813189e0342fa78d3a0e7057.zip llvm-d2fd0d3cbc2e3fbd813189e0342fa78d3a0e7057.tar.gz llvm-d2fd0d3cbc2e3fbd813189e0342fa78d3a0e7057.tar.bz2 | |
[RISCV] Simplify some code in RISCVDisassembler. NFC
Create X0 register directly instead of passing 0 to DecodeGPRRegisterClass.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 014d102..818837d 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -401,7 +401,7 @@ static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { - DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + Inst.addOperand(MCOperand::createReg(RISCV::X0)); uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); @@ -413,7 +413,7 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { - DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + Inst.addOperand(MCOperand::createReg(RISCV::X0)); Inst.addOperand(Inst.getOperand(0)); uint64_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); |