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| author | Garvit Gupta <quic_garvgupt@quicinc.com> | 2023-06-26 11:36:00 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-06-26 11:36:00 -0700 |
| commit | 4c37d30e22ae655394c8b3a7e292c06d393b9b44 (patch) | |
| tree | 386e546dd9e5de66d64262966322eb2a1af84a18 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 4a32581f3dc74a01c3981b51c7dcf66fd7305c00 (diff) | |
| download | llvm-4c37d30e22ae655394c8b3a7e292c06d393b9b44.zip llvm-4c37d30e22ae655394c8b3a7e292c06d393b9b44.tar.gz llvm-4c37d30e22ae655394c8b3a7e292c06d393b9b44.tar.bz2 | |
[RISCV] Add support for custom instructions for Sifive S76.
Support for below instruction is added
1. CFLUSH.D.L1
2. CDISCARD.D.L1
3. CEASE
Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.
Spec - https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153370
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index cc1996a..e6ea6ba 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,6 +558,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, + "Sifive CIE custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); |