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| author | Job Noorman <jnoorman@igalia.com> | 2023-03-23 12:17:57 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@igalia.com> | 2023-03-23 12:32:25 +0000 |
| commit | c39dd7c1db97fa367cb6282067b74cd8e55ef09a (patch) | |
| tree | e05b477d13931c145000b478da9763186c2e06aa /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 6aa7cc037f2f95c237c1d82c523f8857fa3a10c3 (diff) | |
| download | llvm-c39dd7c1db97fa367cb6282067b74cd8e55ef09a.zip llvm-c39dd7c1db97fa367cb6282067b74cd8e55ef09a.tar.gz llvm-c39dd7c1db97fa367cb6282067b74cd8e55ef09a.tar.bz2 | |
[RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.
Differential Revision: https://reviews.llvm.org/D143570
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 15352c1..2d01d6d 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -61,9 +61,9 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() { static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { - bool IsRV32E = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRV32E); + bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE); - if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) + if (RegNo >= 32 || (IsRVE && RegNo >= 16)) return MCDisassembler::Fail; MCRegister Reg = RISCV::X0 + RegNo; |