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| author | melonedo <funanzeng@gmail.com> | 2023-06-11 00:18:17 +0800 |
|---|---|---|
| committer | melonedo <funanzeng@gmail.com> | 2023-07-28 16:52:32 +0800 |
| commit | 3c0604b224e3c38b8db67d55320a0423bb4e8f49 (patch) | |
| tree | 93aeeaa16a83e5853d497071fe1a6a4ba65e006c /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | b395e91f2ef41e44c99857b5dd4e241a57d12b76 (diff) | |
| download | llvm-3c0604b224e3c38b8db67d55320a0423bb4e8f49.zip llvm-3c0604b224e3c38b8db67d55320a0423bb4e8f49.tar.gz llvm-3c0604b224e3c38b8db67d55320a0423bb4e8f49.tar.bz2 | |
[RISCV] Add support for XCVsimd extension in CV32E40P
Implement XCVsimd intrinsics for CV32E40P according to the specification.
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153721
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 05770680..fc5f271 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -567,6 +567,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "CORE-V MAC custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32, "CORE-V ALU custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32, + "CORE-V SIMD extensions custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |