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| author | melonedo <funanzeng@gmail.com> | 2023-07-28 21:32:46 +0800 |
|---|---|---|
| committer | melonedo <funanzeng@gmail.com> | 2023-07-28 21:54:10 +0800 |
| commit | afb9c04a5a44e62f945cd2f667706ded9facd8e3 (patch) | |
| tree | b16fc1fb51a215095a848574283555e48177e773 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 37ca2f56e00a3903f82afd8699c09994b9ef2b8e (diff) | |
| download | llvm-afb9c04a5a44e62f945cd2f667706ded9facd8e3.zip llvm-afb9c04a5a44e62f945cd2f667706ded9facd8e3.tar.gz llvm-afb9c04a5a44e62f945cd2f667706ded9facd8e3.tar.bz2 | |
[RISCV] Add support for XCVbi extension in CV32E40P
Implement XCVbi intrinsics for CV32E40P according to the specification.
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj.
bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited.
e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in.
This commit removed the conflict marker and recommitted.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154412
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index fc5f271..c02c4b1 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -569,6 +569,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "CORE-V ALU custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32, "CORE-V SIMD extensions custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, + "CORE-V Immediate Branching custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |