diff options
| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-17 19:45:55 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-17 19:45:55 +0100 |
| commit | 16a66af0a0fed21b13100afc9cff89db7235ea20 (patch) | |
| tree | 014ed166f5952cd5bd22baff6c524c16359d15fa /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 6774ba841145195c490531bcbfe334b338ec779b (diff) | |
| download | llvm-16a66af0a0fed21b13100afc9cff89db7235ea20.zip llvm-16a66af0a0fed21b13100afc9cff89db7235ea20.tar.gz llvm-16a66af0a0fed21b13100afc9cff89db7235ea20.tar.bz2 | |
Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension"
This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 099d755..b379976 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -369,10 +369,6 @@ static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, - uint64_t Address, - const MCDisassembler *Decoder); - #include "RISCVGenDisassemblerTables.inc" static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, @@ -433,32 +429,6 @@ static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, return MCDisassembler::Success; } -static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, - uint64_t Address, - const MCDisassembler *Decoder) { - uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5); - uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5); - uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5); - uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2); - DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder); - DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder); - (void)Result; - assert(Result == MCDisassembler::Success && "Invalid immediate"); - - // Disassemble the final operand which is implicit. - unsigned Opcode = Inst.getOpcode(); - bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD || - Opcode == RISCV::TH_SWD); - if (IsWordOp) { - Inst.addOperand(MCOperand::createImm(3)); - } else { - Inst.addOperand(MCOperand::createImm(4)); - } - return MCDisassembler::Success; -} - DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -529,13 +499,6 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } - if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadMemPair]) { - LLVM_DEBUG(dbgs() << "Trying XTHeadMemPair custom opcode table:\n"); - Result = decodeInstruction(DecoderTableTHeadMemPair32, MI, Insn, Address, - this, STI); - if (Result != MCDisassembler::Fail) - return Result; - } if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) { LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n"); Result = |