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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-24 21:25:23 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-24 21:40:42 +0100 |
| commit | f68f04d07c69049a95a5f43b5d001ee5a2c87338 (patch) | |
| tree | d1dc6f6947a6d69614598f3ac4daf6da7beee374 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | bfeef8b794da7510cd410c87ebc81e231c4450b3 (diff) | |
| download | llvm-f68f04d07c69049a95a5f43b5d001ee5a2c87338.zip llvm-f68f04d07c69049a95a5f43b5d001ee5a2c87338.tar.gz llvm-f68f04d07c69049a95a5f43b5d001ee5a2c87338.tar.bz2 | |
[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144681
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index eccaa9d..15352c1 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -520,6 +520,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.hasFeature(RISCV::FeatureVendorXTHeadCondMov)) { + LLVM_DEBUG(dbgs() << "Trying XTHeadCondMov custom opcode table:\n"); + Result = decodeInstruction(DecoderTableTHeadCondMov32, MI, Insn, Address, + this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } if (STI.hasFeature(RISCV::FeatureVendorXTHeadCmo)) { LLVM_DEBUG(dbgs() << "Trying XTHeadCmo custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadCmo32, MI, Insn, Address, |