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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-08 01:08:11 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-08 07:54:52 +0100 |
| commit | e25b30d90a69846650fa15a3e41a013ea20193ff (patch) | |
| tree | 213b5c9a1a9e430a5b798e00d760edf80e0819c2 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | a13645cf8c9ac403d4fa8da29a74392a4777b245 (diff) | |
| download | llvm-e25b30d90a69846650fa15a3e41a013ea20193ff.zip llvm-e25b30d90a69846650fa15a3e41a013ea20193ff.tar.gz llvm-e25b30d90a69846650fa15a3e41a013ea20193ff.tar.bz2 | |
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba. It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBa is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143029
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 17a8d48..bf60cd1 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -471,6 +471,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBa]) { + LLVM_DEBUG(dbgs() << "Trying XTHeadBa custom opcode table:\n"); + Result = decodeInstruction(DecoderTableTHeadBa32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) + return Result; + } if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) { LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n"); Result = |