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path: root/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-03-18[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)quic_hchandel1-6/+6
2025-03-17[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)Craig Topper1-10/+8
2025-03-13[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)u4f31-2/+3
2025-03-12[RISCV][Disassembler] Use a table to store all the decoder tables and their a...Craig Topper1-70/+100
2025-03-10[RISCV] Merge DecoderNamespace for CORE-V extensions. NFCCraig Topper1-14/+8
2025-03-10[RISCV] Merge DecoderNamespace for T-Head extensions. NFC (#130555)Craig Topper1-22/+10
2025-03-06[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)users/mariusz-sikora-at-amd/testquic_hchandel1-5/+27
2025-02-27[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)Craig Topper1-19/+13
2025-02-26[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)Sam Elliott1-1/+3
2025-02-26[RISCV][MC] Add assembler support for XRivosVisni (#128773)Philip Reames1-3/+6
2025-02-25[RISCV] Merge some of the Sifive decoder tables. (#128794)Craig Topper1-20/+13
2025-02-25[RISCV][NFC] Merge Xqci Decoder Tables (#128140)Sam Elliott1-28/+21
2025-02-25[RISCV] Correctly Decode Unsigned Immediates with Ranges (#128584)Sam Elliott1-0/+13
2025-02-24[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)quic_hchandel1-0/+2
2025-02-21[RISCV] Assembler support for XRivosVizip (#127694)Philip Reames1-0/+3
2025-02-21[RISCV] Simplify the debug messages in the disassembler. (#128102)Craig Topper1-78/+63
2025-02-06[RISCV][Disassemble] Ensure the comment stream of the disassembler is set. (#...Francesco Petrogalli1-0/+1
2025-01-28[RISCV] Add MIPS extensions (#121394)Djordje Todorovic1-0/+5
2025-01-24[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317)Min-Yih Hsu1-0/+10
2025-01-23[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)quic_hchandel1-2/+26
2025-01-13[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)quic_hchandel1-0/+4
2025-01-07[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)quic_hchandel1-0/+5
2025-01-03[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)Sudharsan Veeravalli1-0/+3
2024-12-29[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#12...quic_hchandel1-0/+6
2024-12-14[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)Sudharsan Veeravalli1-0/+2
2024-12-12[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)quic_hchandel1-0/+2
2024-12-01[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)Sudharsan Veeravalli1-0/+2
2024-11-29[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)Sudharsan Veeravalli1-0/+2
2024-11-28[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)Sudharsan Veeravalli1-0/+2
2024-11-08[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)Craig Topper1-0/+21
2024-10-06[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)Craig Topper1-0/+10
2024-10-01[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)Craig Topper1-0/+13
2024-09-26[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)Craig Topper1-0/+13
2024-09-10[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d al...Craig Topper1-2/+7
2024-07-11[RISCV] Add QingKe "XW" compressed opcode extension (#97925)R1-0/+3
2024-04-29[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)Craig Topper1-5/+37
2024-04-26[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit vers...Craig Topper1-99/+119
2024-04-26[RISCV] Fix off by 1 typo in decodeVMaskReg. NFCCraig Topper1-2/+2
2024-04-26[RISCV] Consistently use uint32_t in Disassembler decode functions. NFCCraig Topper1-6/+6
2024-04-19[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)Craig Topper1-1/+1
2024-03-13[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions....Craig Topper1-0/+8
2024-02-06[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variab...Yeting Kuo1-10/+10
2024-01-10[RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#...Craig Topper1-0/+4
2024-01-09[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)Craig Topper1-1/+1
2023-12-30[RISCV] Add MC layer support for Zicfiss. (#66043)Yeting Kuo1-0/+27
2023-12-28[RISCV] Remove XSfcie extension.Craig Topper1-2/+0
2023-12-27[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)Yeting Kuo1-2/+0
2023-11-16[RISCV][MC] MC layer support for xcvmem and xcvelw extensionsLiaoChunyu1-0/+16
2023-11-03[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)Brandon Wu1-0/+3
2023-11-03[RISCV] Support Xsfvfwmaccqqq extensions (#68296)Brandon Wu1-0/+3
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