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| author | Nelson Chu <nelson.chu@sifive.com> | 2022-04-14 21:25:36 -0700 |
|---|---|---|
| committer | 4vtomat <brandon.wu@sifive.com> | 2023-04-09 20:41:01 -0700 |
| commit | 0b9a620b832e3a493de0e550ac00a1903129092d (patch) | |
| tree | 8486a620ca30cceaf799e3840c49c5815d681a6b /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | aa18091124b24f25c84371dff1134ccc9adba145 (diff) | |
| download | llvm-0b9a620b832e3a493de0e550ac00a1903129092d.zip llvm-0b9a620b832e3a493de0e550ac00a1903129092d.tar.gz llvm-0b9a620b832e3a493de0e550ac00a1903129092d.tar.bz2 | |
[RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf
Differential Revision: https://reviews.llvm.org/D144530
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index b6e5838..2121a0e 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -576,6 +576,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.hasFeature(RISCV::FeatureVendorXSfvcp)) { + LLVM_DEBUG(dbgs() << "Trying SiFive VCIX custom opcode table:\n"); + Result = decodeInstruction(DecoderTableXSfvcp32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) + return Result; + } LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); |