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| author | Qihan Cai <qcai8733@uni.sydney.edu.au> | 2023-06-21 22:59:30 +0800 |
|---|---|---|
| committer | QIHAN CAI <qcai8733@uni.sydney.edu.au> | 2023-06-21 23:08:49 +0800 |
| commit | e219dd88d1b61153805742587a9ed7f96b9faecc (patch) | |
| tree | 2da583c64c579a0ca96454617109300c74a64ecc /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 7b80a322ab702a4a17fdf8488cdfb29a5b08a027 (diff) | |
| download | llvm-e219dd88d1b61153805742587a9ed7f96b9faecc.zip llvm-e219dd88d1b61153805742587a9ed7f96b9faecc.tar.gz llvm-e219dd88d1b61153805742587a9ed7f96b9faecc.tar.bz2 | |
[RISCV] Add support for XCVmac extension in CV32E40P
Implement XCVmac intrinsics for CV32E40P according to the specification.
This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].
Contributors: @CharKeaney, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj
Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst
[0] https://github.com/openhwgroup/corev-llvm-project
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152821
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 202bfb4..cc1996a 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -561,6 +561,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32, + "CORE-V MAC custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |