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author | melonedo <funanzeng@gmail.com> | 2023-06-14 21:42:57 +0800 |
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committer | melonedo <funanzeng@gmail.com> | 2023-06-19 21:16:07 +0800 |
commit | c5a412dad5b89996cdd1661075c63dbf884f8e5c (patch) | |
tree | 6f3932d813d6c6d140f35e8eba248a4d59180b92 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
parent | c7d3c84449f403716a8866e50491a1860a935b30 (diff) | |
download | llvm-c5a412dad5b89996cdd1661075c63dbf884f8e5c.zip llvm-c5a412dad5b89996cdd1661075c63dbf884f8e5c.tar.gz llvm-c5a412dad5b89996cdd1661075c63dbf884f8e5c.tar.bz2 |
[RISCV] Add support for XCVbitmanip extension in CV32E40P
Implement XCVbitmanip intrinsics for CV32E40P according to the specification.
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj.
Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152915
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index e10fb7d..202bfb4 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,6 +558,9 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, + DecoderTableXCVbitmanip32, + "CORE-V Bit Manipulation custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |