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| author | melonedo <funanzeng@gmail.com> | 2023-07-28 19:28:20 +0800 |
|---|---|---|
| committer | melonedo <funanzeng@gmail.com> | 2023-07-28 19:28:20 +0800 |
| commit | e4777dc4b9cb371971523cc603e1b8a5c7255e7e (patch) | |
| tree | eb3c0fd7004ece4a22629932678b06d4cf3ff36f /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9092acc510108737e0e9e3857756a65032debc6f (diff) | |
| download | llvm-e4777dc4b9cb371971523cc603e1b8a5c7255e7e.zip llvm-e4777dc4b9cb371971523cc603e1b8a5c7255e7e.tar.gz llvm-e4777dc4b9cb371971523cc603e1b8a5c7255e7e.tar.bz2 | |
Revert "[RISCV] Add support for XCVbi extension in CV32E40P"
This reverts commit bf2ad26b4ff856aab9a62ad168e6bdefeedc374f as it
checked in merge conflict markers.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index c02c4b1..fc5f271 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -569,8 +569,6 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "CORE-V ALU custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32, "CORE-V SIMD extensions custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, - "CORE-V Immediate Branching custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |