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| author | Brandon Wu <brandon.wu@sifive.com> | 2023-10-20 11:16:20 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-20 11:16:20 +0800 |
| commit | d1985e3d1fedeb68a7d0d07d654e9c4fb1473989 (patch) | |
| tree | f6ab6292d3aa413950f95f8f33232d7e526343f4 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9d10fbbb299eae4a63f1028274e2ffe92bf8e75a (diff) | |
| download | llvm-d1985e3d1fedeb68a7d0d07d654e9c4fb1473989.zip llvm-d1985e3d1fedeb68a7d0d07d654e9c4fb1473989.tar.gz llvm-d1985e3d1fedeb68a7d0d07d654e9c4fb1473989.tar.bz2 | |
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
SiFive Int8 Matrix Multiplication Extensions Specification
https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad6011259_int8-matmul-spec.pdf
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index d561d90..e5ce029 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,6 +558,12 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custom opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32, + "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32, + "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, "Sifive CIE custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, |