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path: root/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
7 days[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)Rux1241-2/+2
7 days[TableGen][DecoderEmitter][RISCV] Always handle `bits<0>` (#159951)Sergei Barannikov1-0/+8
2025-09-15[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483)Sergei Barannikov1-40/+24
2025-09-12[RISCV][MC] Add MC support of Zibi experimental extension (#127463)Boyao Wang1-0/+8
2025-09-11[RISCV] Fix GPRPairNoX0 Disassembly (#158001)Sam Elliott1-0/+9
2025-09-04[RISCV] Remove post-decoding instruction adjustments (#156360)Sergei Barannikov1-17/+8
2025-09-02[MC][DecoderEmitter] Fix build warning: explicit specialization cannot have a...Rahul Joshi1-3/+5
2025-09-01[AMDGPU, RISCV] Fix warningsKazu Hirata1-3/+3
2025-09-01[RISCV] Fix -Wexplicit-specialization-storage-class warningsFangrui Song1-3/+3
2025-09-01[LLVM][MC][DecoderEmitter] Add support to specialize decoder per bitwidth (#1...Rahul Joshi1-7/+9
2025-09-01[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for...UmeshKalappa1-7/+8
2025-08-22[NFC][MC][RISCV] Rearrange decoder functions for RISCV disassembler (#154998)Rahul Joshi1-10/+2
2025-08-22[RISCV] Add initial assembler/MC layer support for big-endian (#146534)Djordje Todorovic1-0/+4
2025-08-21[NFC][MC][Decoder] Extract fixed pieces of decoder code into new header file ...Rahul Joshi1-0/+2
2025-08-18[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (#151706)林克1-0/+3
2025-08-08[RISCV] Move the decoder table for XCV, Xqci and XRivos from standard section...Jim Lin1-3/+3
2025-07-28[RISCV] Move definitions of decodeZcmpRlist/decodeXqccmpRlistS0 to their decl...Craig Topper1-23/+15
2025-07-25[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructi...Craig Topper1-105/+6
2025-07-15[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)Jim Lin1-1/+2
2025-07-07[RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)Jim Lin1-1/+2
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa1-0/+3
2025-07-01[RISCV] Use uint64_t for Insn in getInstruction32 and getInstruction16. NFC (...Craig Topper1-2/+6
2025-06-18[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension ...Jim Lin1-2/+2
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
2025-05-21[RISCV] Add MC layer support for XSfmm*. (#133031)Craig Topper1-3/+36
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-0/+11
2025-05-15[RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (#139849)Jim Lin1-1/+2
2025-05-12[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (#138827)Jim Lin1-1/+2
2025-04-28[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)Jim Lin1-6/+9
2025-04-15[RISCV] Fix xmipscmov extension name (#135647)Djordje Todorovic1-2/+2
2025-04-04[RISCV] Make decodeXqccmpRlistS0 defer to decodeZcmpRlist after checking for ...Craig Topper1-4/+2
2025-04-04[RISCV] Remove unused function declaration. NFCCraig Topper1-3/+0
2025-04-04[RISCV] Rename Spimm to StackAdj in most places. NFCCraig Topper1-8/+2
2025-04-02[RISCV] Modify register type of extd* Xqcibm instructions (#134027)Sudharsan Veeravalli1-0/+10
2025-03-31[RISCV] Use decodeCLUIImmOperand when disassembling C_LUI_HINT. (#133789)Craig Topper1-8/+21
2025-03-31[RISCV] Correct disassembly of cm.push/pop for RVE. (#133816)Craig Topper1-6/+12
2025-03-31[RISCV] Prevent disassembling RVC hint instructions with x16-x31 for RVE. (#1...Craig Topper1-14/+24
2025-03-31[RISCV] Use decodeUImmLog2XLenNonZeroOperand in decodeRVCInstrRdRs1UImm. NFC ...Craig Topper1-15/+11
2025-03-31[RISCV] For RV32C, disassembly of c.slli should fail when immediate > 31 (#13...Paul Bowen-Huggett1-4/+8
2025-03-28[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)quic_hchandel1-9/+9
2025-03-28[RISCV] Remove unnecessary if guard before calling SignExtend64<6> in decodeC...Craig Topper1-2/+1
2025-03-28[RISCV] Fix the disassembler's handling of C.LUI when imm=0 (#133450)Paul Bowen-Huggett1-2/+3
2025-03-27[RISCV][Xqccmp] Correctly Parse/Disassemble pushfp (#133188)Sam Elliott1-1/+12
2025-03-26[RISCV] Use named sub-operands to simplify encoding/decoding for CoreV Reg-Re...Craig Topper1-12/+0
2025-03-22Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" ...Sudharsan Veeravalli1-8/+18
2025-03-21Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)"Kazu Hirata1-18/+8
2025-03-22[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)quic_hchandel1-8/+18
2025-03-20[RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (#131996)quic_hchandel1-4/+4
2025-03-19[RISCV] Add Zilsd and Zclsd Extensions (#131094)dong-miao1-0/+16
2025-03-18[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)Sudharsan Veeravalli1-1/+2
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