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| author | Manolis Tsamis <manolis.tsamis@vrull.eu> | 2023-02-22 10:36:42 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-22 10:57:48 +0100 |
| commit | f5b484c56f7b0bbf265c06de70ed0c432543847f (patch) | |
| tree | 213ed229fd0f000f44a729126fbe8e1260ed2325 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | abc1f3329831606b06a934bba8ac3fc3df522e07 (diff) | |
| download | llvm-f5b484c56f7b0bbf265c06de70ed0c432543847f.zip llvm-f5b484c56f7b0bbf265c06de70ed0c432543847f.tar.gz llvm-f5b484c56f7b0bbf265c06de70ed0c432543847f.tar.bz2 | |
[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144496
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index cb7b229..d7c7fcc 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -520,6 +520,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.hasFeature(RISCV::FeatureVendorXTHeadCmo)) { + LLVM_DEBUG(dbgs() << "Trying XTHeadCmo custom opcode table:\n"); + Result = decodeInstruction(DecoderTableTHeadCmo32, MI, Insn, Address, + this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) { LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address, |