diff options
| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-13 16:29:31 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-13 17:02:09 +0100 |
| commit | fc02eeb24fc024aa05fc2d58b73b713dc5bfd166 (patch) | |
| tree | bb962b973b21eaf2cae2924f31c4822d29059d0f /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | b8c2ba138ef689710efaa6331a618620058057fb (diff) | |
| download | llvm-fc02eeb24fc024aa05fc2d58b73b713dc5bfd166.zip llvm-fc02eeb24fc024aa05fc2d58b73b713dc5bfd166.tar.gz llvm-fc02eeb24fc024aa05fc2d58b73b713dc5bfd166.tar.bz2 | |
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBb is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143036
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143439
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 7276d82..647607a66 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -478,6 +478,13 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (Result != MCDisassembler::Fail) return Result; } + if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBb]) { + LLVM_DEBUG(dbgs() << "Trying XTHeadBb custom opcode table:\n"); + Result = decodeInstruction(DecoderTableTHeadBb32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) + return Result; + } if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadBs]) { LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n"); Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this, |