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| author | Craig Topper <craig.topper@sifive.com> | 2023-02-05 12:31:36 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-02-05 12:31:36 -0800 |
| commit | b3ab26b4aa2fe242218b1c0cfae9420f2c4021fa (patch) | |
| tree | 68ae1e680e04cf7f88624bb898ed2fb0caab4567 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | dd0caa82de593f080469c772b5b092e1bf7f7cc0 (diff) | |
| download | llvm-b3ab26b4aa2fe242218b1c0cfae9420f2c4021fa.zip llvm-b3ab26b4aa2fe242218b1c0cfae9420f2c4021fa.tar.gz llvm-b3ab26b4aa2fe242218b1c0cfae9420f2c4021fa.tar.bz2 | |
[RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_ADDI.
And was then printed as 'mv'.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 42cdd75..014d102 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -349,6 +349,10 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, return MCDisassembler::Success; } +static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); + static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder); @@ -371,6 +375,18 @@ static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, #include "RISCVGenDisassemblerTables.inc" +static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 7, 5); + DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid register"); + Inst.addOperand(Inst.getOperand(0)); + Inst.addOperand(MCOperand::createImm(0)); + return MCDisassembler::Success; +} + static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { |