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| author | Qihan Cai <qcai8733@uni.sydney.edu.au> | 2023-07-20 14:37:05 +0800 |
|---|---|---|
| committer | QIHAN CAI <qcai8733@uni.sydney.edu.au> | 2023-07-28 11:37:31 +0800 |
| commit | 092e60a3fcb642e0a1d08c4c30722995573c7d4d (patch) | |
| tree | 51f33508468ee6d25f17ca86e7818481670c3982 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 3da76c2116179fdb3fff8feb4551209e4218746e (diff) | |
| download | llvm-092e60a3fcb642e0a1d08c4c30722995573c7d4d.zip llvm-092e60a3fcb642e0a1d08c4c30722995573c7d4d.tar.gz llvm-092e60a3fcb642e0a1d08c4c30722995573c7d4d.tar.bz2 | |
[RISCV] Add support for XCValu extension in CV32E40P
Implement XCValu intrinsics for CV32E40P according to the specification.
This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153748
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index e6ea6ba..05770680 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -565,6 +565,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "CORE-V Bit Manipulation custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32, "CORE-V MAC custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32, + "CORE-V ALU custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |