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2020-03-10Merge pull request #417 from chihminchao/rvv-fix-2020-03-09Andrew Waterman7-355/+437
Rvv fix 2020 03 09
2020-03-09op: rvv: update encodingChih-Min Chao1-315/+372
change to 0ce3ec1 1. mstatus.vs is changed and it is 0.9 draft feature 2. opcodes are separated into difference files by extensions. The opcodes are not modifed but order are differenct. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09commitlog: enhance vector dumpChih-Min Chao2-5/+17
1. don't duplicate vconfig for lmul >=2 case 2. add l# to show prenset vl value Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09rvv: enhance --varch to parse string type optionsZhen Wei3-34/+46
To improve the readability of varch argument and future configuration, the format of options within varch are changed from "v128:e64:s512" to "vlen:128,elen:64,slen:512".
2020-03-09rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
The spec doesn't limit the range of middle value. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-05Make debug printfs only show in debug builds. (#414)Andrew Waterman1-6/+6
2020-03-04Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
2020-02-28Merge branch 'rswarbrick-mcountinhibit'Andrew Waterman2-0/+3
2020-02-28Add do-nothing support for mcountinhibit CSRRupert Swarbrick2-0/+3
This CSR appeared in version 1.11 of the ISA and is described in the Volume II: Privileged Architecture manual. It's an optional register and should read as zero if not implemented, which is what this patch does.
2020-02-28Enable SOFTFLOAT_ROUND_ODD for vfncvt.rod.f.f.wAndrew Waterman1-0/+1
2020-02-27Merge pull request #405 from riscv/mstatus-sxl-uxlUdit Khanna1-7/+8
Check presence of [S|U] extension for mstatus.[sxl|uxl] read/write
2020-02-27Check presence of [S|U] extension for mstatus.[sxl|uxl] read/writeUdit Khanna1-7/+8
2020-02-27Merge pull request #406 from rswarbrick/cflagsAndrew Waterman6-24/+325
Allow overriding CFLAGS and similar when building
2020-02-27Allow overriding CFLAGS and similar when buildingRupert Swarbrick6-24/+325
Before this patch, I don't think it was possible to change (say) CFLAGS as part of running the make command. Nor did setting them when running configure do anything. Getting this right is a little fiddly: for example, see Automake's approach at [1] ("AM_CFLAGS" and friends). This patch adds an "mcppbs-" prefix, and sets things up properly for CFLAGS, CPPFLAGS, CXXFLAGS and LDFLAGS. Note that the bulk of the patch is either the auto-generated configure script or the ax_*.m4 files vendored in from the autoconf archive (needed to handle --export-dynamic correctly without trashing settings from the user running configure). What's supposed to happen is as follows: - Base compilation flags that should apply to everything (standard optimisation flags, warning flags etc.) are defined in Makefile.in. - When the user runs configure, they can set compilation flags on the command line. These end up as environment variables in the shell script. - Compilation flags that can only be decided when we run configure (this is currently just whether we support -Wl,--export-dynamic) are appended to the configure-time LDFLAGS environment variable. - At the end of the configure script, these environment variables are spliced into Makefile.in to fill out the corresponding @<varname>@ entries. - When running make, the user might again override compilation flags. These will get appended to the flags found so far. As a concrete example: mkdir build cd build ../configure CXXFLAGS='-O3' make CXXFLAGS='-O0' will result in c++ compile commands that look like this: g++ -MMD -MP \ -DPREFIX=\"/usr/local\" -Wall -Wno-unused -g -O2 -std=c++11 \ -O3 \ -O0 \ -I. -I.. -I../fesvr -I../riscv -I../dummy_rocc -I../softfloat \ -I../spike_main -fPIC -c ../fesvr/elfloader.cc (I've added some newlines to wrap the long line). Note that we have the base flags from Makefile.in (called $(default-CXXFLAGS) there) first. Then we have the -O3 from the configure command. Finally we have the -O0 from the Make command line. And I can finally run "make CXXFLAGS='-O0 -g3'". Phew! [1] https://www.gnu.org/software/automake/manual/html_node/Flag-Variables-Ordering.html
2020-02-21Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-02-21Initialize some uninitialized stateAndrew Waterman2-1/+4
2020-02-20Disallow access to debug memory region unless in debug modeAndrew Waterman2-3/+31
... as recommended, but not required, by the spec.
2020-02-20Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
38438778f0fc34df8cdf748cc9f35e1d15e0c8db fixed the bug. cc @timsifive
2020-02-20Merge pull request #403 from chihminchao/rvv-fix-2020-02-20Andrew Waterman6-10/+3
Rvv fix 2020 02 20
2020-02-20rvv: only check segment overlapping in index loadChih-Min Chao1-4/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20rvv: also relax vmerge_vim/vvm when lmul = 1Chih-Min Chao2-2/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20rvv: also relax lmul in vfwredumChih-Min Chao2-2/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
cc @chihminchao @HanKuanChen
2020-02-18Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman5-13/+20
Since vector stores read rd, rather than write rd, there is no overlap constraint.
2020-02-18Merge pull request #396 from chihminchao/rvv-fix-2020-02-14Andrew Waterman17-25/+31
Rvv fix 2020 02 14
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18rvv: make variable name match its meaningChih-Min Chao4-4/+4
zimm5 for unsigned and zero-extended simm5 for signed and signed-extended It is unsigned arithmetics Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extensionChih-Min Chao3-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-17v[f]merge: allow v0 overlap if LMUL = 1Andrew Waterman2-2/+0
The VI_CHECK_SSS macro enforces the weaker constraint.
2020-02-17vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
The spec says, "For vadc and vsbc, an illegal instruction exception is raised if the destination vector register is v0 and LMUL > 1." cc @chihminchao @HanKuanChen
2020-02-15Merge branch 'avpatel-real_time_clint_v1'Andrew Waterman5-8/+35
2020-02-15Make CLINT API use Hz instead of MHzAndrew Waterman3-6/+6
2020-02-15Add optional support for real-time clintAnup Patel5-8/+35
This patch adds optional support clint timer incrementing at real-time rate. This can be enabled by passing command line parameter "--real-time-clint". This feature can be used for: 1. Checking whether any code addition to Spike is slowing down simulation too much 2. Comparing run-time for software on Spike with other functional simulators (such as QEMU) Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-14rvv: fix exception rethrow in fault-first loadChih-Min Chao1-1/+1
rethrow the original exception rather than a copied one Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-14rvv: reset vstart to 0 when vmv.s.x and vmv.x.s and also check the vstart < ↵Dave.Wen2-1/+5
vl in vmv.s.x
2020-02-14rvv: respect vstart in fault-first loadChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-14rvv: vms[bio]f.m need to start from 0Chih-Min Chao3-6/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-14rvv: vsbc/vmsbc behavior of the sub orderMax Lin4-4/+4
2020-02-14rvv: fix Vxrm not reflected in fcsrDave.Wen1-2/+7
2020-02-13Merge branch 'avpatel-linux_boot_v1'Andrew Waterman5-5/+56
2020-02-14Make spike capable of booting LinuxAnup Patel5-5/+56
Latest Linux does not boot Spike mainly because: 1. Spike does not set bootargs in DTS 2. Spike does not provide mechanism to load initrd for Linux This patch addresses both above issues and we can now get latest Linux to prompt on Spike. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-12Improve --varch error checking. (#394)Tim Newsome3-12/+22
* Improve --varch error checking. Print out why an option has problems. Add check that elen must be >= xlen, flen, per the spec. Since RV32G includes D by default, bump default elen to 64. * Remove debug printf.
2020-02-11Merge pull request #393 from riscv/fesvr-dmactive-before-readAndrew Waterman1-3/+3
FESVR: ensure dmactive is 1 before reading debug module registers
2020-02-11FESVR: ensure dmactive is 1 before reading debug module registersMegan Wachs1-3/+3
2020-02-10Merge pull request #392 from riscv/fesvr-no-dm-when-dmactive-0Andrew Waterman1-1/+1
FESVR: Can't read a DM register when DMACTIVE=0
2020-02-10FESVR: Can't read a DM register when DMACTIVE=0Megan Wachs1-1/+1
2020-02-06Fix incorrect commentsAndrew Waterman2-2/+2
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