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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-11 15:20:44 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-11 15:20:44 -0600 |
| commit | 78344a5a2c88c4c313b8b216bd76f31792812205 (patch) | |
| tree | 6d1a7c0bfd88f2d96b4e8efdb9a7d762837eeb24 | |
| parent | ab141b814daf778597b106c155fd8c011be90f10 (diff) | |
| parent | b8eb9cd50da527d8ac280f818baa5473ab21da91 (diff) | |
| download | riscv-isa-sim-78344a5a2c88c4c313b8b216bd76f31792812205.zip riscv-isa-sim-78344a5a2c88c4c313b8b216bd76f31792812205.tar.gz riscv-isa-sim-78344a5a2c88c4c313b8b216bd76f31792812205.tar.bz2 | |
Merge pull request #393 from riscv/fesvr-dmactive-before-read
FESVR: ensure dmactive is 1 before reading debug module registers
| -rw-r--r-- | fesvr/dtm.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc index 46032c3..6e4952f 100644 --- a/fesvr/dtm.cc +++ b/fesvr/dtm.cc @@ -558,6 +558,9 @@ void dtm_t::producer_thread() // Learn about the Debug Module and assert things we // depend on in this code. + // Enable the debugger. + write(DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); + // These are checked every time we run an abstract command. uint32_t abstractcs = read(DMI_ABSTRACTCS); ram_words = get_field(abstractcs, DMI_ABSTRACTCS_PROGSIZE); @@ -571,9 +574,6 @@ void dtm_t::producer_thread() assert(get_field(hartinfo, DMI_HARTINFO_DATAACCESS)); data_base = get_field(hartinfo, DMI_HARTINFO_DATAADDR); - - // Enable the debugger. - write(DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); num_harts = enumerate_harts(); halt(0); |