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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-26 21:26:28 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-09 00:02:20 -0700 |
| commit | aa1392d063cf52685f33e5c8d2a6b42a04ede948 (patch) | |
| tree | e648df75e4042a61a59dc03888cafdd9b4b86243 | |
| parent | a19971fff9f2938fd381c17b11b69908bc598175 (diff) | |
| download | riscv-isa-sim-aa1392d063cf52685f33e5c8d2a6b42a04ede948.zip riscv-isa-sim-aa1392d063cf52685f33e5c8d2a6b42a04ede948.tar.gz riscv-isa-sim-aa1392d063cf52685f33e5c8d2a6b42a04ede948.tar.bz2 | |
rvv: vstart must be 0 for reduction instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 81ec1ad..0dd6975 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -502,6 +502,7 @@ static inline bool is_overlapped(const int astart, const int asize, require(P.VU.vsew * 2 <= P.VU.ELEN); \ } \ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ + require(P.VU.vstart == 0); \ // // vector: loop header and end helper |