Vector stores don't care if rd overlaps v0 (#400)

Since vector stores read rd, rather than write rd, there is no overlap
constraint.

5 files changed, 20 insertions, 13 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 505cda5..bbcc37a 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -415,7 +415,7 @@ static inline bool is_overlapped(const int astart, const int asize,
   if (insn.v_vm() == 0) \
     require(insn.rd() != 0);
 
-#define VI_CHECK_LDST_INDEX \
+#define VI_CHECK_ST_INDEX \
   require_vector; \
   require((insn.rd() & (P.VU.vlmul - 1)) == 0); \
   require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
@@ -424,6 +424,11 @@ static inline bool is_overlapped(const int astart, const int asize,
   if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \
     require(insn.rd() != 0); \
 
+#define VI_CHECK_LD_INDEX \
+  VI_CHECK_ST_INDEX; \
+  if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \
+    require(insn.rd() != 0); \
+
 #define VI_CHECK_MSS(is_vs1) \
   if (P.VU.vlmul > 1) { \
     require(!is_overlapped(insn.rd(), 1, insn.rs2(), P.VU.vlmul)); \
@@ -445,12 +450,14 @@ static inline bool is_overlapped(const int astart, const int asize,
       require(insn.rd() != 0); \
   }
 
-#define VI_CHECK_SXX \
+#define VI_CHECK_STORE_SXX \
   require_vector; \
-  if (P.VU.vlmul > 1) { \
-    require((insn.rd() & (P.VU.vlmul - 1)) == 0); \
-    if (insn.v_vm() == 0) \
-      require(insn.rd() != 0); \
+  require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+
+#define VI_CHECK_SXX \
+  VI_CHECK_STORE_SXX; \
+  if (P.VU.vlmul > 1 && insn.v_vm() == 0) { \
+    require(insn.rd() != 0); \
   }
 
 #define VI_CHECK_DSS(is_vs1) \
@@ -1540,15 +1547,15 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   VI_LD_COMMON(stride, offset, ld_width, elt_byte)
 
 #define VI_LD_INDEX(stride, offset, ld_width, elt_byte) \
-  VI_CHECK_LDST_INDEX; \
+  VI_CHECK_LD_INDEX; \
   VI_LD_COMMON(stride, offset, ld_width, elt_byte)
 
 #define VI_ST(stride, offset, st_width, elt_byte) \
-  VI_CHECK_SXX; \
+  VI_CHECK_STORE_SXX; \
   VI_ST_COMMON(stride, offset, st_width, elt_byte) \
 
 #define VI_ST_INDEX(stride, offset, st_width, elt_byte) \
-  VI_CHECK_LDST_INDEX; \
+  VI_CHECK_ST_INDEX; \
   VI_ST_COMMON(stride, offset, st_width, elt_byte) \
 
 #define VI_LDST_FF(itype, tsew) \
diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h
index 03f1980..cee0282 100644
--- a/riscv/insns/vsuxb_v.h
+++ b/riscv/insns/vsuxb_v.h
@@ -1,6 +1,6 @@
 // vsuxb.v and vsxseg[2-8]b.v
 require(P.VU.vsew >= e8);
-VI_CHECK_SXX;
+VI_CHECK_STORE_SXX;
 require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
 reg_t vl = P.VU.vl;
 reg_t baseAddr = RS1;
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
index 22d6fb5..438ca6a 100644
--- a/riscv/insns/vsuxe_v.h
+++ b/riscv/insns/vsuxe_v.h
@@ -2,7 +2,7 @@
 const reg_t sew = P.VU.vsew;
 const reg_t vl = P.VU.vl;
 require(sew >= e8 && sew <= e64);
-VI_CHECK_SXX;
+VI_CHECK_STORE_SXX;
 require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
 reg_t baseAddr = RS1;
 reg_t stride = insn.rs2();
diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h
index a34bc27..28d2d91 100644
--- a/riscv/insns/vsuxh_v.h
+++ b/riscv/insns/vsuxh_v.h
@@ -1,6 +1,6 @@
 // vsxh.v and vsxseg[2-8]h.v
 require(P.VU.vsew >= e16);
-VI_CHECK_SXX;
+VI_CHECK_STORE_SXX;
 require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
 reg_t vl = P.VU.vl;
 reg_t baseAddr = RS1;
diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h
index f42092d..0ee1f4b 100644
--- a/riscv/insns/vsuxw_v.h
+++ b/riscv/insns/vsuxw_v.h
@@ -1,6 +1,6 @@
 // vsxw.v and vsxseg[2-8]w.v
 require(P.VU.vsew >= e32);
-VI_CHECK_SXX;
+VI_CHECK_STORE_SXX;
 require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
 reg_t vl = P.VU.vl;
 reg_t baseAddr = RS1;