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| author | Dave.Wen <dave.wen@sifive.com> | 2020-02-11 23:28:19 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 01:48:42 -0800 |
| commit | bb786db8b87915ec9a9f5d1278753032a6363be1 (patch) | |
| tree | 29d6d9ee4f4b05c6352a146bd8930c9baaa3e02e | |
| parent | ab141b814daf778597b106c155fd8c011be90f10 (diff) | |
| download | riscv-isa-sim-bb786db8b87915ec9a9f5d1278753032a6363be1.zip riscv-isa-sim-bb786db8b87915ec9a9f5d1278753032a6363be1.tar.gz riscv-isa-sim-bb786db8b87915ec9a9f5d1278753032a6363be1.tar.bz2 | |
rvv: fix Vxrm not reflected in fcsr
| -rw-r--r-- | riscv/processor.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f92bb2b..961514b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -846,10 +846,15 @@ reg_t processor_t::get_csr(int which) break; return state.frm; case CSR_FCSR: - require_fp; + {require_fp; if (!supports_extension('F')) break; - return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); + uint32_t shared_flags = 0; + if (supports_extension('V')) + shared_flags = (VU.vxrm << FSR_VXRM_SHIFT) | (VU.vxsat << FSR_VXSAT_SHIFT); + return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT) | + shared_flags; + } case CSR_INSTRET: case CSR_CYCLE: if (ctr_ok) |