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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-19 20:48:26 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-20 01:50:28 -0800 |
| commit | aa0754e093dd2efb0c7a244125dd05937b2d12c3 (patch) | |
| tree | 1e056b7b9154963167435a57852f2188066d3027 | |
| parent | 6d0c5a9050269da4702ba482ba12a1f5a13de28a (diff) | |
| download | riscv-isa-sim-aa0754e093dd2efb0c7a244125dd05937b2d12c3.zip riscv-isa-sim-aa0754e093dd2efb0c7a244125dd05937b2d12c3.tar.gz riscv-isa-sim-aa0754e093dd2efb0c7a244125dd05937b2d12c3.tar.bz2 | |
rvv: don't zero vstart in the beginning
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 85c4e06..1372b9a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1569,7 +1569,6 @@ for (reg_t i = 0; i < vlmax; ++i) { \ bool early_stop = false; \ const reg_t vlmul = P.VU.vlmul; \ require(rd_num + nf * P.VU.vlmul <= NVPR); \ - p->VU.vstart = 0; \ for (reg_t i = p->VU.vstart; i < vl; ++i) { \ VI_STRIP(i); \ VI_ELEMENT_SKIP(i); \ |