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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 19:39:30 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-09 00:02:20 -0700 |
| commit | ef5950ea11c4ef97bbe9a025a70950f754b38959 (patch) | |
| tree | 8020233d5f3fb422e7c33348bfb79ea8aac365ec | |
| parent | aa1392d063cf52685f33e5c8d2a6b42a04ede948 (diff) | |
| download | riscv-isa-sim-ef5950ea11c4ef97bbe9a025a70950f754b38959.zip riscv-isa-sim-ef5950ea11c4ef97bbe9a025a70950f754b38959.tar.gz riscv-isa-sim-ef5950ea11c4ef97bbe9a025a70950f754b38959.tar.bz2 | |
rvv: handle middle value of vslidedown.vx
The spec doesn't limit the range of middle value.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/insns/vslidedown_vx.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vslidedown_vx.h b/riscv/insns/vslidedown_vx.h index 9881e0e..744a7a5 100644 --- a/riscv/insns/vslidedown_vx.h +++ b/riscv/insns/vslidedown_vx.h @@ -4,7 +4,7 @@ require((insn.rd() & (P.VU.vlmul - 1)) == 0); if (P.VU.vlmul > 1 && insn.v_vm() == 0) require(insn.rd() != 0); -const reg_t sh = RS1; +const uint128_t sh = RS1; VI_LOOP_BASE reg_t offset = 0; |