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| author | Max Lin <max.lin@sifive.com> | 2020-02-12 18:18:56 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 01:48:48 -0800 |
| commit | 169dfe7cebcec8a7200fc9c26bbbbaf1ab1a8081 (patch) | |
| tree | 9478763a5a227009721a42bf3af8256c3f2d4573 | |
| parent | bb786db8b87915ec9a9f5d1278753032a6363be1 (diff) | |
| download | riscv-isa-sim-169dfe7cebcec8a7200fc9c26bbbbaf1ab1a8081.zip riscv-isa-sim-169dfe7cebcec8a7200fc9c26bbbbaf1ab1a8081.tar.gz riscv-isa-sim-169dfe7cebcec8a7200fc9c26bbbbaf1ab1a8081.tar.bz2 | |
rvv: vsbc/vmsbc behavior of the sub order
| -rw-r--r-- | riscv/insns/vmsbc_vvm.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vmsbc_vxm.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vsbc_vvm.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vsbc_vxm.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/riscv/insns/vmsbc_vvm.h b/riscv/insns/vmsbc_vvm.h index ef8304b..2f41f01 100644 --- a/riscv/insns/vmsbc_vvm.h +++ b/riscv/insns/vmsbc_vvm.h @@ -6,7 +6,7 @@ VI_VV_LOOP_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0; - uint128_t res = (op_mask & vs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & vs1) - carry; carry = (res >> sew) & 0x1u; vd = (vd & ~mmask) | ((carry << mpos) & mmask); diff --git a/riscv/insns/vmsbc_vxm.h b/riscv/insns/vmsbc_vxm.h index c0e8ba2..87ce085 100644 --- a/riscv/insns/vmsbc_vxm.h +++ b/riscv/insns/vmsbc_vxm.h @@ -6,7 +6,7 @@ VI_XI_LOOP_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0; - uint128_t res = (op_mask & rs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & rs1) - carry; carry = (res >> sew) & 0x1u; vd = (vd & ~mmask) | ((carry << mpos) & mmask); diff --git a/riscv/insns/vsbc_vvm.h b/riscv/insns/vsbc_vvm.h index 314077d..96b8bb8 100644 --- a/riscv/insns/vsbc_vvm.h +++ b/riscv/insns/vsbc_vvm.h @@ -5,6 +5,6 @@ VI_VV_LOOP_WITH_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = (v0 >> mpos) & 0x1; - uint128_t res = (op_mask & vs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & vs1) - carry; vd = res; }) diff --git a/riscv/insns/vsbc_vxm.h b/riscv/insns/vsbc_vxm.h index f8555ab..c6f9ca8 100644 --- a/riscv/insns/vsbc_vxm.h +++ b/riscv/insns/vsbc_vxm.h @@ -5,6 +5,6 @@ VI_XI_LOOP_WITH_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = (v0 >> mpos) & 0x1; - uint128_t res = (op_mask & rs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & rs1) - carry; vd = res; }) |