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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-18 23:17:05 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-18 23:17:05 -0800 |
| commit | 6d0c5a9050269da4702ba482ba12a1f5a13de28a (patch) | |
| tree | db718a88a9a327c9c8ff7143fd476701c794a69f | |
| parent | 78bbcb94c25b15e27d7414db2a121d28c57d7af0 (diff) | |
| download | riscv-isa-sim-6d0c5a9050269da4702ba482ba12a1f5a13de28a.zip riscv-isa-sim-6d0c5a9050269da4702ba482ba12a1f5a13de28a.tar.gz riscv-isa-sim-6d0c5a9050269da4702ba482ba12a1f5a13de28a.tar.bz2 | |
widening reductions are legal when LMUL=8
cc @chihminchao @HanKuanChen
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bbcc37a..85c4e06 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -501,7 +501,6 @@ static inline bool is_overlapped(const int astart, const int asize, #define VI_CHECK_REDUCTION(is_wide) \ require_vector;\ if (is_wide) {\ - require(P.VU.vlmul <= 4); \ require(P.VU.vsew * 2 <= P.VU.ELEN); \ } \ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ |