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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 20:24:49 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-09 19:59:47 -0700 |
| commit | 2be050171015bb662a4495422c9e31f0be8a9c3a (patch) | |
| tree | ee2ba637dab51239bbc3294175fd16c9ce30d518 | |
| parent | c949a75893a3c8df98a407d216ee995c82d4db4f (diff) | |
| download | riscv-isa-sim-2be050171015bb662a4495422c9e31f0be8a9c3a.zip riscv-isa-sim-2be050171015bb662a4495422c9e31f0be8a9c3a.tar.gz riscv-isa-sim-2be050171015bb662a4495422c9e31f0be8a9c3a.tar.bz2 | |
commitlog: enhance vector dump
1. don't duplicate vconfig for lmul >=2 case
2. add l# to show prenset vl value
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 3 | ||||
| -rw-r--r-- | riscv/execute.cc | 19 |
2 files changed, 17 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 0dd6975..73514dc 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -167,6 +167,7 @@ private: #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) +# define WRITE_VSTATUS #else /* 0 : int * 1 : floating @@ -182,6 +183,7 @@ private: STATE.log_reg_write[((reg) << 2) | 1] = wdata; \ DO_WRITE_FREG(reg, wdata); \ }) +# define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; #endif // RVC macros @@ -231,6 +233,7 @@ private: require_vector_vs; \ require_extension('V'); \ require(!P.VU.vill); \ + WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); #define require_vector_for_vsetvl \ diff --git a/riscv/execute.cc b/riscv/execute.cc index 6e897ec..12dd781 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -63,6 +63,7 @@ static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) fprintf(stderr, " ("); commit_log_print_value(insn.length() * 8, 0, insn.bits()); fprintf(stderr, ")"); + bool show_vec = false; for (auto item : reg) { if (item.first == 0) @@ -72,6 +73,7 @@ static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) int size; int rd = item.first >> 2; bool is_vec = false; + bool is_vreg = false; switch (item.first & 3) { case 0: size = xlen; @@ -84,6 +86,9 @@ static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) case 2: size = p->VU.VLEN; prefix = 'v'; + is_vreg = true; + break; + case 3: is_vec = true; break; default: @@ -91,14 +96,18 @@ static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) break; } - if (is_vec) - fprintf(stderr, " e%ld m%ld", p->VU.vsew, p->VU.vlmul); + if (!show_vec && (is_vreg || is_vec)) { + fprintf(stderr, " e%ld m%ld l%ld", p->VU.vsew, p->VU.vlmul, p->VU.vl); + show_vec = true; + } - fprintf(stderr, " %c%2d ", prefix, rd); - if (is_vec) + if (!is_vec) { + fprintf(stderr, " %c%2d ", prefix, rd); + if (is_vreg) commit_log_print_value(size, &p->VU.elt<uint8_t>(rd, 0)); - else + else commit_log_print_value(size, item.second.v[1], item.second.v[0]); + } } for (auto item : load) { |