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| author | Tim Newsome <tim@sifive.com> | 2020-02-12 16:14:08 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-12 18:14:08 -0600 |
| commit | 6baf42ac1d93c82ff59669c00a6a8991e3b7e4e1 (patch) | |
| tree | 83947d5fc69b453372f4068aba5d978b33c81e27 | |
| parent | 78344a5a2c88c4c313b8b216bd76f31792812205 (diff) | |
| download | riscv-isa-sim-6baf42ac1d93c82ff59669c00a6a8991e3b7e4e1.zip riscv-isa-sim-6baf42ac1d93c82ff59669c00a6a8991e3b7e4e1.tar.gz riscv-isa-sim-6baf42ac1d93c82ff59669c00a6a8991e3b7e4e1.tar.bz2 | |
Improve --varch error checking. (#394)
* Improve --varch error checking.
Print out why an option has problems.
Add check that elen must be >= xlen, flen, per the spec.
Since RV32G includes D by default, bump default elen to 64.
* Remove debug printf.
| -rwxr-xr-x | configure | 4 | ||||
| -rw-r--r-- | riscv/processor.cc | 26 | ||||
| -rw-r--r-- | riscv/riscv.ac | 4 |
3 files changed, 22 insertions, 12 deletions
@@ -1362,7 +1362,7 @@ Optional Packages: --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) --with-isa=RV64IMAFDC Sets the default RISC-V ISA --with-priv=MSU Sets the default RISC-V privilege modes supported - --with-varch=v128:e32:s128 + --with-varch=v128:e64:s128 Sets the default vector config Some influential environment variables: @@ -4649,7 +4649,7 @@ _ACEOF else cat >>confdefs.h <<_ACEOF -#define DEFAULT_VARCH "v128:e32:s128" +#define DEFAULT_VARCH "v128:e64:s128" _ACEOF fi diff --git a/riscv/processor.cc b/riscv/processor.cc index f92bb2b..a926021 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -68,9 +68,9 @@ static void bad_priv_string(const char* priv) abort(); } -static void bad_varch_string(const char* varch) +static void bad_varch_string(const char* varch, const char *message) { - fprintf(stderr, "error: bad --varch option %s\n", varch); + fprintf(stderr, "error: bad --varch option %s: %s\n", varch, message); abort(); } @@ -80,9 +80,9 @@ static int parse_varch(std::string &str){ std::string sval = str.substr(1); val = std::stoi(sval); if ((val & (val - 1)) != 0) // val should be power of 2 - bad_varch_string(str.c_str()); + bad_varch_string(str.c_str(), "must be a power of 2"); }else{ - bad_varch_string(str.c_str()); + bad_varch_string(str.c_str(), "must not be empty"); } return val; } @@ -114,14 +114,24 @@ void processor_t::parse_varch_string(const char* s) }else if (token[0] == 's'){ slen = parse_varch(token); }else{ - bad_varch_string(str.c_str()); + bad_varch_string(str.c_str(), "Unsupported token"); } str.erase(0, pos + delimiter.length()); } - if (!(vlen >= 32 || vlen <= 4096) && !(slen >= vlen || slen <= vlen) && !(elen >= slen || elen <= slen)){ - bad_varch_string(s); - } + /* Vector spec requirements. */ + if (vlen < elen) + bad_varch_string(s, "vlen must be >= elen"); + if (vlen < slen) + bad_varch_string(s, "vlen must be >= slen"); + if (slen < 32) + bad_varch_string(s, "slen must be >= 32"); + if ((unsigned) elen < std::max(max_xlen, get_flen())) + bad_varch_string(s, "elen must be >= max(xlen, flen)"); + + /* spike requirements. */ + if (vlen > 4096) + bad_varch_string(s, "vlen must be <= 4096"); VU.VLEN = vlen; VU.ELEN = elen; diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 747c3e3..fc45732 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -13,10 +13,10 @@ AC_ARG_WITH(priv, AC_DEFINE_UNQUOTED([DEFAULT_PRIV], "MSU", [Default value for --priv switch])) AC_ARG_WITH(varch, - [AS_HELP_STRING([--with-varch=v128:e32:s128], + [AS_HELP_STRING([--with-varch=v128:e64:s128], [Sets the default vector config])], AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "$withval", [Default value for --varch switch]), - AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "v128:e32:s128", [Default value for --varch switch])) + AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "v128:e64:s128", [Default value for --varch switch])) AC_SEARCH_LIBS([dlopen], [dl dld], [], [ |