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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-21 12:12:57 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-21 12:12:57 -0800 |
| commit | b1563b8af6bd44cf8dd2190c7695b8fe4310c268 (patch) | |
| tree | 82cc197bfb7b5ae80f8a3a944f4764ff1bc65293 | |
| parent | 1ef875316adee8174fe2cf83317f59019d3c1aa2 (diff) | |
| download | riscv-isa-sim-b1563b8af6bd44cf8dd2190c7695b8fe4310c268.zip riscv-isa-sim-b1563b8af6bd44cf8dd2190c7695b8fe4310c268.tar.gz riscv-isa-sim-b1563b8af6bd44cf8dd2190c7695b8fe4310c268.tar.bz2 | |
Initialize some uninitialized state
| -rw-r--r-- | riscv/debug_module.cc | 3 | ||||
| -rw-r--r-- | riscv/processor.cc | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index f5d33f2..499f552 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -43,7 +43,8 @@ debug_module_t::debug_module_t(sim_t *sim, const debug_module_config_t &config) // The spec lets a debugger select nonexistent harts. Create hart_state for // them because I'm too lazy to add the code to just ignore accesses. hart_state(1 << field_width(sim->nprocs())), - hart_array_mask(sim->nprocs()) + hart_array_mask(sim->nprocs()), + rti_remaining(0) { D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start)); D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start)); diff --git a/riscv/processor.cc b/riscv/processor.cc index 383fd3f..e4a5f6c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -262,6 +262,8 @@ void state_t::reset(reg_t max_isa) memset(this->tdata2, 0, sizeof(this->tdata2)); debug_mode = false; + single_step = STEP_NONE; + memset(this->mcontrol, 0, sizeof(this->mcontrol)); memset(this->pmpcfg, 0, sizeof(this->pmpcfg)); memset(this->pmpaddr, 0, sizeof(this->pmpaddr)); |