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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-12 23:36:47 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 01:49:13 -0800 |
| commit | b41a465767999de2d33ed3f30e2cb6965d809fdd (patch) | |
| tree | aee709d56927177f22792dc5fa7dbd23a5806b01 | |
| parent | 76a5262667ecece7df35c10ef670de4af0e3a481 (diff) | |
| download | riscv-isa-sim-b41a465767999de2d33ed3f30e2cb6965d809fdd.zip riscv-isa-sim-b41a465767999de2d33ed3f30e2cb6965d809fdd.tar.gz riscv-isa-sim-b41a465767999de2d33ed3f30e2cb6965d809fdd.tar.bz2 | |
rvv: respect vstart in fault-first load
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index cd2bde3..bc24275 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1564,7 +1564,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ const reg_t vlmul = P.VU.vlmul; \ require(rd_num + nf * P.VU.vlmul <= NVPR); \ p->VU.vstart = 0; \ - for (reg_t i = 0; i < vl; ++i) { \ + for (reg_t i = p->VU.vstart; i < vl; ++i) { \ VI_STRIP(i); \ VI_ELEMENT_SKIP(i); \ \ @@ -1600,8 +1600,8 @@ for (reg_t i = 0; i < vlmax; ++i) { \ if (early_stop) { \ break; \ } \ - } - + } \ + p->VU.vstart = 0; // // vector: vfp helper |