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author | Andrew Waterman <andrew@sifive.com> | 2020-02-18 11:10:56 -0800 |
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committer | GitHub <noreply@github.com> | 2020-02-18 11:10:56 -0800 |
commit | 722b9bf869b7928b060201a794406bcf32a4d532 (patch) | |
tree | be2cf70460b304ceace00ae0f79f16ccf75e97d8 | |
parent | 77b98bf87e768eeea7aa1f93cb270843e5cb7b2a (diff) | |
parent | 4a0ad01f700460a1587581305b8007cc8936663e (diff) | |
download | riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.zip riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.tar.gz riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.tar.bz2 |
Merge pull request #396 from chihminchao/rvv-fix-2020-02-14
Rvv fix 2020 02 14
-rw-r--r-- | riscv/decode.h | 10 | ||||
-rw-r--r-- | riscv/execute.cc | 2 | ||||
-rw-r--r-- | riscv/insns/vmsbc_vvm.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsbc_vxm.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsbf_m.h | 3 | ||||
-rw-r--r-- | riscv/insns/vmsgtu_vi.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsif_m.h | 3 | ||||
-rw-r--r-- | riscv/insns/vmsleu_vi.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsof_m.h | 3 | ||||
-rw-r--r-- | riscv/insns/vmv_s_x.h | 4 | ||||
-rw-r--r-- | riscv/insns/vmv_x_s.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsaddu_vi.h | 4 | ||||
-rw-r--r-- | riscv/insns/vsbc_vvm.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsbc_vxm.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsrl_vi.h | 2 | ||||
-rw-r--r-- | riscv/insns/vssrl_vi.h | 2 | ||||
-rw-r--r-- | riscv/processor.cc | 9 |
17 files changed, 31 insertions, 25 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index eb72dab..505cda5 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -613,7 +613,7 @@ static inline bool is_overlapped(const int astart, const int asize, #define VI_U_PARAMS(x) \ type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ - type_usew_t<x>::type simm5 = (type_usew_t<x>::type)insn.v_zimm5(); \ + type_usew_t<x>::type zimm5 = (type_usew_t<x>::type)insn.v_zimm5(); \ type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); #define VV_PARAMS(x) \ @@ -1564,7 +1564,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ const reg_t vlmul = P.VU.vlmul; \ require(rd_num + nf * P.VU.vlmul <= NVPR); \ p->VU.vstart = 0; \ - for (reg_t i = 0; i < vl; ++i) { \ + for (reg_t i = p->VU.vstart; i < vl; ++i) { \ VI_STRIP(i); \ VI_ELEMENT_SKIP(i); \ \ @@ -1574,7 +1574,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ val = MMU.load_##itype##tsew(baseAddr + (i * nf + fn) * (tsew / 8)); \ } catch (trap_t& t) { \ if (i == 0) \ - throw t; /* Only take exception on zeroth element */ \ + throw; /* Only take exception on zeroth element */ \ /* Reduce VL if an exception occurs on a later element */ \ early_stop = true; \ P.VU.vl = i; \ @@ -1600,8 +1600,8 @@ for (reg_t i = 0; i < vlmax; ++i) { \ if (early_stop) { \ break; \ } \ - } - + } \ + p->VU.vstart = 0; // // vector: vfp helper diff --git a/riscv/execute.cc b/riscv/execute.cc index 974ad7f..cff8496 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -92,7 +92,7 @@ static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) } if (is_vec) - fprintf(stderr, " e%d m%d", p->VU.vsew >> 3, p->VU.vlmul); + fprintf(stderr, " e%ld m%ld", p->VU.vsew >> 3, p->VU.vlmul); fprintf(stderr, " %c%2d ", prefix, rd); if (is_vec) diff --git a/riscv/insns/vmsbc_vvm.h b/riscv/insns/vmsbc_vvm.h index ef8304b..2f41f01 100644 --- a/riscv/insns/vmsbc_vvm.h +++ b/riscv/insns/vmsbc_vvm.h @@ -6,7 +6,7 @@ VI_VV_LOOP_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0; - uint128_t res = (op_mask & vs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & vs1) - carry; carry = (res >> sew) & 0x1u; vd = (vd & ~mmask) | ((carry << mpos) & mmask); diff --git a/riscv/insns/vmsbc_vxm.h b/riscv/insns/vmsbc_vxm.h index c0e8ba2..87ce085 100644 --- a/riscv/insns/vmsbc_vxm.h +++ b/riscv/insns/vmsbc_vxm.h @@ -6,7 +6,7 @@ VI_XI_LOOP_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0; - uint128_t res = (op_mask & rs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & rs1) - carry; carry = (res >> sew) & 0x1u; vd = (vd & ~mmask) | ((carry << mpos) & mmask); diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index fd352ea..356ed2b 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -1,6 +1,7 @@ // vmsbf.m vd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector; +require(P.VU.vstart == 0); reg_t vl = P.VU.vl; reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); @@ -29,5 +30,3 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) { vd = (vd & ~mmask) | ((res << mpos) & mmask); } } - -P.VU.vstart = 0; diff --git a/riscv/insns/vmsgtu_vi.h b/riscv/insns/vmsgtu_vi.h index ad8449a..ee47e50 100644 --- a/riscv/insns/vmsgtu_vi.h +++ b/riscv/insns/vmsgtu_vi.h @@ -1,5 +1,5 @@ // vsgtu.vi vd, vd2, simm5 VI_VI_ULOOP_CMP ({ - res = vs2 > simm5; + res = vs2 > (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); }) diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index 0896095..366c926 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -1,6 +1,7 @@ // vmpopc rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector; +require(P.VU.vstart == 0); reg_t vl = P.VU.vl; reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); @@ -29,5 +30,3 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) { vd = (vd & ~mmask) | ((res << mpos) & mmask); } } - -P.VU.vstart = 0; diff --git a/riscv/insns/vmsleu_vi.h b/riscv/insns/vmsleu_vi.h index 78f7740..d11ff6a 100644 --- a/riscv/insns/vmsleu_vi.h +++ b/riscv/insns/vmsleu_vi.h @@ -1,5 +1,5 @@ // vsleu.vi vd, vs2, simm5 VI_VI_ULOOP_CMP ({ - res = vs2 <= simm5; + res = vs2 <= (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); }) diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index 26a89f0..2481c0b 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -1,6 +1,7 @@ // vmsof.m rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector; +require(P.VU.vstart == 0); reg_t vl = P.VU.vl; reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); @@ -27,5 +28,3 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) { vd = (vd & ~mmask) | ((res << mpos) & mmask); } } - -P.VU.vstart = 0; diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index 948b5be..99db2a0 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -5,7 +5,7 @@ require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); reg_t vl = P.VU.vl; -if (vl > 0) { +if (vl > 0 && P.VU.vstart < vl) { reg_t rd_num = insn.rd(); reg_t sew = P.VU.vsew; @@ -26,3 +26,5 @@ if (vl > 0) { vl = 0; } + +P.VU.vstart = 0; diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index 50f2e79..086812b 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -26,3 +26,5 @@ if (!(rs1 >= 0 && rs1 < (P.VU.get_vlen() / sew))) { break; } } + +P.VU.vstart = 0; diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index 9d376cc..3f03fd2 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -1,8 +1,8 @@ -// vsaddu vd, vs2, zimm5 +// vsaddu vd, vs2, simm5 VI_VI_ULOOP ({ bool sat = false; - vd = vs2 + simm5; + vd = vs2 + (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); sat = vd < vs2; vd |= -(vd < vs2); diff --git a/riscv/insns/vsbc_vvm.h b/riscv/insns/vsbc_vvm.h index 314077d..96b8bb8 100644 --- a/riscv/insns/vsbc_vvm.h +++ b/riscv/insns/vsbc_vvm.h @@ -5,6 +5,6 @@ VI_VV_LOOP_WITH_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = (v0 >> mpos) & 0x1; - uint128_t res = (op_mask & vs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & vs1) - carry; vd = res; }) diff --git a/riscv/insns/vsbc_vxm.h b/riscv/insns/vsbc_vxm.h index f8555ab..c6f9ca8 100644 --- a/riscv/insns/vsbc_vxm.h +++ b/riscv/insns/vsbc_vxm.h @@ -5,6 +5,6 @@ VI_XI_LOOP_WITH_CARRY const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); uint64_t carry = (v0 >> mpos) & 0x1; - uint128_t res = (op_mask & rs1) - (op_mask & vs2) - carry; + uint128_t res = (op_mask & vs2) - (op_mask & rs1) - carry; vd = res; }) diff --git a/riscv/insns/vsrl_vi.h b/riscv/insns/vsrl_vi.h index 5006854..fe5d272 100644 --- a/riscv/insns/vsrl_vi.h +++ b/riscv/insns/vsrl_vi.h @@ -1,5 +1,5 @@ // vsrl.vi vd, vs2, zimm5 VI_VI_ULOOP ({ - vd = vs2 >> (simm5 & (sew - 1) & 0x1f); + vd = vs2 >> (zimm5 & (sew - 1) & 0x1f); }) diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h index 55e085d..d125164 100644 --- a/riscv/insns/vssrl_vi.h +++ b/riscv/insns/vssrl_vi.h @@ -2,7 +2,7 @@ VRM xrm = P.VU.get_vround_mode(); VI_VI_ULOOP ({ - int sh = simm5 & (sew - 1) & 0x1f; + int sh = zimm5 & (sew - 1) & 0x1f; uint128_t val = vs2; INT_ROUNDING(val, xrm, sh); diff --git a/riscv/processor.cc b/riscv/processor.cc index a926021..383fd3f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -856,10 +856,15 @@ reg_t processor_t::get_csr(int which) break; return state.frm; case CSR_FCSR: - require_fp; + {require_fp; if (!supports_extension('F')) break; - return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); + uint32_t shared_flags = 0; + if (supports_extension('V')) + shared_flags = (VU.vxrm << FSR_VXRM_SHIFT) | (VU.vxsat << FSR_VXSAT_SHIFT); + return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT) | + shared_flags; + } case CSR_INSTRET: case CSR_CYCLE: if (ctr_ok) |