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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-17 14:26:19 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-17 14:26:19 -0800 |
| commit | a562fdb3aa567e8c498c9ea2dd0fb2013057dc6e (patch) | |
| tree | 46230efdeb6fccf58f89689a31c5168c235df3e0 | |
| parent | f406783b136ee99db1b1f3da09176307818d14bd (diff) | |
| download | riscv-isa-sim-a562fdb3aa567e8c498c9ea2dd0fb2013057dc6e.zip riscv-isa-sim-a562fdb3aa567e8c498c9ea2dd0fb2013057dc6e.tar.gz riscv-isa-sim-a562fdb3aa567e8c498c9ea2dd0fb2013057dc6e.tar.bz2 | |
vadc/vsbc: allow v0 overlap if LMUL = 1
The spec says, "For vadc and vsbc, an illegal instruction exception is raised if the destination vector register is v0 and LMUL > 1."
cc @chihminchao @HanKuanChen
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index cd2bde3..eb72dab 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1318,7 +1318,7 @@ VI_LOOP_END VI_LOOP_END #define VI_VV_LOOP_WITH_CARRY(BODY) \ - require(insn.rd() != 0); \ + require(P.VU.vlmul == 1 || insn.rd() != 0); \ VI_CHECK_SSS(true); \ VI_GENERAL_LOOP_BASE \ VI_MASK_VARS \ @@ -1338,7 +1338,7 @@ VI_LOOP_END VI_LOOP_END #define VI_XI_LOOP_WITH_CARRY(BODY) \ - require(insn.rd() != 0); \ + require(P.VU.vlmul == 1 || insn.rd() != 0); \ VI_CHECK_SSS(false); \ VI_GENERAL_LOOP_BASE \ VI_MASK_VARS \ |