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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-04 18:40:43 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-04 18:40:43 -0800 |
| commit | d51edef8a614d689e9b0387f6156feaeded95a91 (patch) | |
| tree | f475198949c9b33b6e41071764e4d8ac1440c579 | |
| parent | fe24c46547f98576e74d3cabd5548a721cb38b3f (diff) | |
| download | riscv-isa-sim-d51edef8a614d689e9b0387f6156feaeded95a91.zip riscv-isa-sim-d51edef8a614d689e9b0387f6156feaeded95a91.tar.gz riscv-isa-sim-d51edef8a614d689e9b0387f6156feaeded95a91.tar.bz2 | |
Don't clobber trigger types when initializing state
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 17b8796..66901a0 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -257,13 +257,13 @@ void state_t::reset(reg_t max_isa) memset(&this->dcsr, 0, sizeof(this->dcsr)); tselect = 0; + memset(this->mcontrol, 0, sizeof(this->mcontrol)); for (auto &item : mcontrol) item.type = 2; memset(this->tdata2, 0, sizeof(this->tdata2)); debug_mode = false; single_step = STEP_NONE; - memset(this->mcontrol, 0, sizeof(this->mcontrol)); memset(this->pmpcfg, 0, sizeof(this->pmpcfg)); memset(this->pmpaddr, 0, sizeof(this->pmpaddr)); |