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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 00:20:04 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 01:49:13 -0800 |
| commit | 923a82f79782062e97229af357d119daedaebe9d (patch) | |
| tree | 6196beae38f38621a67036c92736b6a102650ec2 | |
| parent | 320882e1e403d262c408be28d9329e95eb53909b (diff) | |
| download | riscv-isa-sim-923a82f79782062e97229af357d119daedaebe9d.zip riscv-isa-sim-923a82f79782062e97229af357d119daedaebe9d.tar.gz riscv-isa-sim-923a82f79782062e97229af357d119daedaebe9d.tar.bz2 | |
rvv: fix exception rethrow in fault-first load
rethrow the original exception rather than a copied one
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bc24275..1878478 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1574,7 +1574,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ val = MMU.load_##itype##tsew(baseAddr + (i * nf + fn) * (tsew / 8)); \ } catch (trap_t& t) { \ if (i == 0) \ - throw t; /* Only take exception on zeroth element */ \ + throw; /* Only take exception on zeroth element */ \ /* Reduce VL if an exception occurs on a later element */ \ early_stop = true; \ P.VU.vl = i; \ |