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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 01:30:08 -0800 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-18 09:19:44 -0800 |
commit | eeba38241d4bc9cca1f3b3acfd2564baa51edf76 (patch) | |
tree | 8ffd8fc3a4f107368093127a3818ae1422acbfd5 | |
parent | 6b143cd0a244c5ad38bdbfe88495647496e62dd5 (diff) | |
download | riscv-isa-sim-eeba38241d4bc9cca1f3b3acfd2564baa51edf76.zip riscv-isa-sim-eeba38241d4bc9cca1f3b3acfd2564baa51edf76.tar.gz riscv-isa-sim-eeba38241d4bc9cca1f3b3acfd2564baa51edf76.tar.bz2 |
rvv: make variable name match its meaning
zimm5 for unsigned and zero-extended
simm5 for signed and signed-extended
It is unsigned arithmetics
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/decode.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsaddu_vi.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsrl_vi.h | 2 | ||||
-rw-r--r-- | riscv/insns/vssrl_vi.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1878478..6e8a175 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -613,7 +613,7 @@ static inline bool is_overlapped(const int astart, const int asize, #define VI_U_PARAMS(x) \ type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ - type_usew_t<x>::type simm5 = (type_usew_t<x>::type)insn.v_zimm5(); \ + type_usew_t<x>::type zimm5 = (type_usew_t<x>::type)insn.v_zimm5(); \ type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); #define VV_PARAMS(x) \ diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index 7a200df..3f03fd2 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -1,4 +1,4 @@ -// vsaddu vd, vs2, zimm5 +// vsaddu vd, vs2, simm5 VI_VI_ULOOP ({ bool sat = false; diff --git a/riscv/insns/vsrl_vi.h b/riscv/insns/vsrl_vi.h index 5006854..fe5d272 100644 --- a/riscv/insns/vsrl_vi.h +++ b/riscv/insns/vsrl_vi.h @@ -1,5 +1,5 @@ // vsrl.vi vd, vs2, zimm5 VI_VI_ULOOP ({ - vd = vs2 >> (simm5 & (sew - 1) & 0x1f); + vd = vs2 >> (zimm5 & (sew - 1) & 0x1f); }) diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h index 55e085d..d125164 100644 --- a/riscv/insns/vssrl_vi.h +++ b/riscv/insns/vssrl_vi.h @@ -2,7 +2,7 @@ VRM xrm = P.VU.get_vround_mode(); VI_VI_ULOOP ({ - int sh = simm5 & (sew - 1) & 0x1f; + int sh = zimm5 & (sew - 1) & 0x1f; uint128_t val = vs2; INT_ROUNDING(val, xrm, sh); |