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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-20 00:15:14 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-20 01:50:36 -0800 |
| commit | 192225712c1e2bda558b733c5d3aa5b46df7cc76 (patch) | |
| tree | 7ed0bd86ce31581e2b94ad1e3e5eab2684129605 | |
| parent | 035a6790538c97489c194fce2df3899ae8484f83 (diff) | |
| download | riscv-isa-sim-192225712c1e2bda558b733c5d3aa5b46df7cc76.zip riscv-isa-sim-192225712c1e2bda558b733c5d3aa5b46df7cc76.tar.gz riscv-isa-sim-192225712c1e2bda558b733c5d3aa5b46df7cc76.tar.bz2 | |
rvv: only check segment overlapping in index load
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1372b9a..ee07577 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -419,13 +419,11 @@ static inline bool is_overlapped(const int astart, const int asize, require_vector; \ require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ - if (insn.v_nf() > 0) \ - require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul)); \ - if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \ - require(insn.rd() != 0); \ #define VI_CHECK_LD_INDEX \ VI_CHECK_ST_INDEX; \ + if (insn.v_nf() > 0) \ + require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul)); \ if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \ require(insn.rd() != 0); \ |