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| author | Rahul Joshi <rjoshi@nvidia.com> | 2025-08-22 11:55:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-22 11:55:40 -0700 |
| commit | 34d2e687dced84b5987043714d56331839b8ecac (patch) | |
| tree | 04c3edab1b38598a28774e29f610a5e27d55aeb9 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | f84037ea2e71420f6e3724e9d5409be071dbf115 (diff) | |
| download | llvm-34d2e687dced84b5987043714d56331839b8ecac.zip llvm-34d2e687dced84b5987043714d56331839b8ecac.tar.gz llvm-34d2e687dced84b5987043714d56331839b8ecac.tar.bz2 | |
[NFC][MC][RISCV] Rearrange decoder functions for RISCV disassembler (#154998)
Rearrange decode functions to be before including the generated
disassembler code and eliminate forward declarations for most of them.
This is possible because `fieldFromInstruction` is now in MCDecoder.h
and not in the generated disassembler code.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index ac6684f..dbb16fc 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,16 +558,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, return decodeZcmpRlist(Inst, Imm, Address, Decoder); } -static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, - uint64_t Address, - const MCDisassembler *Decoder); - -static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, - uint64_t Address, - const MCDisassembler *Decoder); - -#include "RISCVGenDisassemblerTables.inc" - static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { @@ -608,6 +598,8 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, return S; } +#include "RISCVGenDisassemblerTables.inc" + // Add implied SP operand for C.*SP compressed instructions. The SP operand // isn't explicitly encoded in the instruction. void RISCVDisassembler::addSPOperands(MCInst &MI) const { |