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| author | UmeshKalappa <103930015+ukalappa-mips@users.noreply.github.com> | 2025-07-03 14:29:10 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-03 10:59:10 +0200 |
| commit | 032966ff5679804e826b76beab6306e277ef8d33 (patch) | |
| tree | 2a2c3bc8db4eb56032c70e4dea074fac24e93e3b /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | bd6cd92984e7a30cb91e4f069a0bacc5c582a234 (diff) | |
| download | llvm-032966ff5679804e826b76beab6306e277ef8d33.zip llvm-032966ff5679804e826b76beab6306e277ef8d33.tar.gz llvm-032966ff5679804e826b76beab6306e277ef8d33.tar.bz2 | |
[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)
the extension enabled with xmipscbop.
Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System
Programmer’s Guide" for more info on the extension at
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 52061e9..aa45e7e 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -790,6 +790,9 @@ static constexpr DecoderListEntry DecoderList32[]{ {DecoderTableXmipscmov32, {RISCV::FeatureVendorXMIPSCMov}, "MIPS mips.ccmov"}, + {DecoderTableXmipscbop32, + {RISCV::FeatureVendorXMIPSCBOP}, + "MIPS mips.pref"}, {DecoderTableXAndes32, XAndesGroup, "Andes extensions"}, // Standard Extensions {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"}, |