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authorKazu Hirata <kazu@google.com>2025-03-21 20:28:11 -0700
committerKazu Hirata <kazu@google.com>2025-03-21 20:28:11 -0700
commitfe7776eab87b3c79372b2056a6e0dd9ef1c4b10e (patch)
treea273961aed22ea082be77cf5fc9f9af8d28f29d1 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
parent3840f787a21a66686f5d8bf61877d41f3a65f205 (diff)
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Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)"
This reverts commit 3840f787a21a66686f5d8bf61877d41f3a65f205. Multiple builtbot failures have been reported: https://github.com/llvm/llvm-project/pull/132184
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
-rw-r--r--llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp26
1 files changed, 8 insertions, 18 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 93cbf66..5abf15a 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -370,15 +370,6 @@ static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
return MCDisassembler::Success;
}
-static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
- int64_t Address,
- const MCDisassembler *Decoder) {
- assert(isUInt<3>(Imm) && "Invalid Slist immediate");
- const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
- Inst.addOperand(MCOperand::createImm(Slist[Imm]));
- return MCDisassembler::Success;
-}
-
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
const MCDisassembler *Decoder) {
@@ -672,15 +663,14 @@ static constexpr FeatureBitset XRivosFeatureGroup = {
};
static constexpr FeatureBitset XqciFeatureGroup = {
- RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
- RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
- RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
- RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
- RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
- RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
- RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
- RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
- RISCV::FeatureVendorXqcisync,
+ RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
+ RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
+ RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
+ RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
+ RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
+ RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
+ RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
+ RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
};
static constexpr FeatureBitset XSfVectorGroup = {