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116 min.[RISCV] Add isel patterns to form vwsll.vx/vi when the LHS is an any_extend. ...Craig Topper1-0/+16
5 hours[PowerPC] Remove NoInfsFPMath uses (#163029)paperchalice1-1/+1
6 hoursReland "[DebugMetadata][DwarfDebug] Support function-local types in lexical b...Vladislav Dzhidzhoev10-108/+305
6 hours[RISCV] Sink some encoding related lets into class/def bodies. NFC (#179544)Craig Topper1-28/+40
7 hoursReapply "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morp...Craig Topper1-8/+17
7 hours[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)Min-Yih Hsu1-5/+19
7 hours[BPF] Replace copy-assign by move-assign in llvm/lib/Target/BPF/ (#179462)serge-sans-paille2-2/+2
7 hours[ArgPromotion] Add DW_CC_nocall to DISubprogram (#178973)yonghong-song1-0/+11
8 hoursRevert "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morph...Craig Topper1-17/+8
8 hours[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo i...Craig Topper1-8/+17
8 hours[VPlan] Refine exit select check in transformtoPartialReduction.Florian Hahn2-6/+14
8 hours[VPlan] Generalize `VPAllSuccessorsIterator` to support predecessors (#178724)Andrei Elovikov1-62/+104
10 hours[GOFF] Add emission of debug sections (#178677)Kai Nacke1-0/+61
10 hours[llvm][AsmPrinter] Call graph section Flag field enum (#176309)Prabhu Rajasekaran1-11/+0
10 hours[AIX] Implement the ifunc attribute. (#153049)Wael Yehia9-33/+419
10 hours[NFC][TableGen] Adopt CodeGenHelpers in IntrinsicEmitter (#179310)Rahul Joshi1-10/+0
11 hours[LLVM][Intrinsics] Minor cleanup in getIntrinsicInfoTableEntries (#179317)Rahul Joshi1-4/+7
11 hours[AMDGPU] Clear no convergence flag on operand folding. NFCI (#179438)Stanislav Mekhanoshin1-0/+2
11 hours[SPIR-V] Add lowering for G_FSINCOS (#179053)Dmitry Sidorov2-0/+63
11 hoursReapply "[InstCombine] Always fold alignment assumptions into operand bundles...Nikolas Klauser1-3/+2
11 hoursARM: Avoid using isTarget wrappers around Triple predicates (#179512)Matt Arsenault2-22/+31
11 hours[InstCombine] fold icmp ne (and X, 1), 0 --> trunc X to i1 (#178977)Andreas Jonson1-5/+2
11 hours[X86] mayFoldIntoVector - recognise larger than legal logic ops may fold to v...Simon Pilgrim1-4/+6
12 hours[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp...Syadus Sefat1-5/+20
12 hoursInstCombine: Handle minnum/maxnum in SimplifyDemandedFPClass (#179299)Matt Arsenault1-3/+11
12 hours[InlineCost] Replace getAllocatedType with getAllocationSize (#178355)Jameson Nash1-11/+12
12 hours[AMDGPU][GlobalISel] Add tbuffer store d16 RegBankLegalize rule (#179411)vangthao951-1/+2
12 hours[X86] Restrict offset folding into address mode in 16-bit mode (#179399)Fangrui Song1-0/+5
12 hours[CodeGen][AArch64] ptrauth intrinsic to safely construct relative ptr (#142047)Abhay Kanhere5-18/+175
12 hours[AMDGPU][Scheduler] Fix incorrect region index in EXPENSIVE_CHECKS (#179461)Lucas Ramirez1-31/+28
13 hours[InstCombine] Fold select of intrinsic into intrinsic of select (#178002)Gauravsingh Sisodia2-0/+49
13 hours[InstCombine] Extend canonicalization of addition to positive numbers (#179343)SiliconA-Z1-22/+66
13 hours[OpenMPOpt] avoid OOB array write (#178686)Jameson Nash1-2/+5
14 hours[RISCV] Wrap some long lines in RISCVInstrInfoV.td. NFCCraig Topper1-7/+10
14 hours[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)Kito Cheng4-19/+38
14 hours[LegalizeTypes] Don't promote operands to VP extends (#179475)Luke Lau2-74/+27
14 hours[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVIns...Craig Topper2-55/+46
15 hoursReland "[BasicBlockUtils] Fix dominator tree update for entry block in splitB...Mingjie Xu2-45/+21
15 hours[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)serge-sans-paille8-13/+13
15 hours[AArch64][PAC] Mark $Scratch operand of AUTxMxN as earlyclobber (#173999)Anatoly Trosinenko1-1/+12
15 hours[SLP]Disable modeling disjoint reduction or as bitcast for big endianAlexey Bataev1-1/+1
15 hours[AMDGPU] Implement llvm.sponentry (#176357)Diana Picus9-10/+99
16 hoursReland "[CoroCleanup] Noop coroutine elision for load-and-call pattern (#1791...Weibo He1-24/+78
17 hours[VPlan] Always set flags for overflowing ops etc via VPIRFlags. (#179138)Florian Hahn8-80/+174
18 hoursRevert "[SeparateConstOffsetFromGEP] Decompose constant xor operand if possib...Eli Friedman1-81/+4
18 hours[AArch64][SME] Limit where SME ABI optimizations apply (#179273)Benjamin Maxwell1-150/+18
18 hours[AMDGPU][SROA] Unify cast chain implementations (#177945)Steffen Larsen3-150/+94
19 hoursAttributor: Add -light options to -attributor-enable flag (#179346)Matt Arsenault1-2/+12
19 hours[AArch64] Fix cttz.elts codegen for fixed-length vectors (#178902)Graham Hunter3-31/+36
19 hours[SelectionDAG] Use promoted types when creating nodes after type legalization...ZhaoQi1-0/+7
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