aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib
AgeCommit message (Expand)AuthorFilesLines
77 min.[AIX] Implement the ifunc attribute. (#153049)HEADmainWael Yehia9-33/+419
96 min.[NFC][TableGen] Adopt CodeGenHelpers in IntrinsicEmitter (#179310)Rahul Joshi1-10/+0
105 min.[LLVM][Intrinsics] Minor cleanup in getIntrinsicInfoTableEntries (#179317)Rahul Joshi1-4/+7
105 min.[AMDGPU] Clear no convergence flag on operand folding. NFCI (#179438)Stanislav Mekhanoshin1-0/+2
113 min.[SPIR-V] Add lowering for G_FSINCOS (#179053)Dmitry Sidorov2-0/+63
2 hoursReapply "[InstCombine] Always fold alignment assumptions into operand bundles...Nikolas Klauser1-3/+2
2 hoursARM: Avoid using isTarget wrappers around Triple predicates (#179512)Matt Arsenault2-22/+31
2 hours[InstCombine] fold icmp ne (and X, 1), 0 --> trunc X to i1 (#178977)Andreas Jonson1-5/+2
3 hours[X86] mayFoldIntoVector - recognise larger than legal logic ops may fold to v...Simon Pilgrim1-4/+6
3 hours[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp...Syadus Sefat1-5/+20
3 hoursInstCombine: Handle minnum/maxnum in SimplifyDemandedFPClass (#179299)Matt Arsenault1-3/+11
3 hours[InlineCost] Replace getAllocatedType with getAllocationSize (#178355)Jameson Nash1-11/+12
3 hours[AMDGPU][GlobalISel] Add tbuffer store d16 RegBankLegalize rule (#179411)vangthao951-1/+2
3 hours[X86] Restrict offset folding into address mode in 16-bit mode (#179399)Fangrui Song1-0/+5
3 hours[CodeGen][AArch64] ptrauth intrinsic to safely construct relative ptr (#142047)Abhay Kanhere5-18/+175
4 hours[AMDGPU][Scheduler] Fix incorrect region index in EXPENSIVE_CHECKS (#179461)Lucas Ramirez1-31/+28
4 hours[InstCombine] Fold select of intrinsic into intrinsic of select (#178002)Gauravsingh Sisodia2-0/+49
4 hours[InstCombine] Extend canonicalization of addition to positive numbers (#179343)SiliconA-Z1-22/+66
5 hours[OpenMPOpt] avoid OOB array write (#178686)Jameson Nash1-2/+5
5 hours[RISCV] Wrap some long lines in RISCVInstrInfoV.td. NFCCraig Topper1-7/+10
5 hours[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)Kito Cheng4-19/+38
5 hours[LegalizeTypes] Don't promote operands to VP extends (#179475)Luke Lau2-74/+27
5 hours[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVIns...Craig Topper2-55/+46
6 hoursReland "[BasicBlockUtils] Fix dominator tree update for entry block in splitB...Mingjie Xu2-45/+21
6 hours[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)serge-sans-paille8-13/+13
6 hours[AArch64][PAC] Mark $Scratch operand of AUTxMxN as earlyclobber (#173999)Anatoly Trosinenko1-1/+12
6 hours[SLP]Disable modeling disjoint reduction or as bitcast for big endianAlexey Bataev1-1/+1
6 hours[AMDGPU] Implement llvm.sponentry (#176357)Diana Picus9-10/+99
7 hoursReland "[CoroCleanup] Noop coroutine elision for load-and-call pattern (#1791...Weibo He1-24/+78
8 hours[VPlan] Always set flags for overflowing ops etc via VPIRFlags. (#179138)Florian Hahn8-80/+174
9 hoursRevert "[SeparateConstOffsetFromGEP] Decompose constant xor operand if possib...Eli Friedman1-81/+4
9 hours[AArch64][SME] Limit where SME ABI optimizations apply (#179273)Benjamin Maxwell1-150/+18
9 hours[AMDGPU][SROA] Unify cast chain implementations (#177945)Steffen Larsen3-150/+94
10 hoursAttributor: Add -light options to -attributor-enable flag (#179346)Matt Arsenault1-2/+12
10 hours[AArch64] Fix cttz.elts codegen for fixed-length vectors (#178902)Graham Hunter3-31/+36
11 hours[SelectionDAG] Use promoted types when creating nodes after type legalization...ZhaoQi1-0/+7
11 hours[llvm][OpenMP] Allow Chunk Size on SIMD Guided (#178853)Jack Styles1-1/+1
12 hours[WebAssembly] Combine shuffle and signed extend to extend_high (#179166)hanbeom1-3/+8
13 hours[HLSL][DXIL][SPIRV] WavePrefixSum intrinsic support (#167946)Kai4-0/+76
13 hours[VPlan] Sink recipes from the vector loop region in licm. (#168031)Mel Chen2-0/+67
13 hoursAttributor: Add denormal-fp-math to attributor-light (#79576)Matt Arsenault1-1/+2
13 hours[RISCV] Pass EEW instead of log2(EEW) to RISCVVXMemOpMC. NFC (#179379)Craig Topper1-10/+10
13 hours[RISCV] Sink conversion from nfields/lmul to nf down one level in RISCVInstrI...Craig Topper1-57/+75
13 hours[AMDGPU] Add SOPK, SOPC and SOPP encoding support for gfx13 (#179179)Mariusz Sikora2-261/+463
14 hours[RISCV] Default all ISD opcodes to Expand for P extension. (#179396)Craig Topper1-5/+15
14 hours[NVPTX] Print PM Event Mask value as unsigned integer. (#178891)Kirill Vedernikov3-1/+20
14 hours[RISCV] Rename VUnitStrideLoadMask->VUnitStrideMaskLoad. NFC (#179360)Craig Topper3-10/+10
14 hours[RISCV] Rename nf->nfields in MC layer. NFC (#179365)Craig Topper2-124/+120
15 hours[RISCV] Add common base classes for loads/stores in RISCVInstrFormatsV.td. NF...Craig Topper1-68/+28
15 hours[NewPM] Fix callsite for x86-lvi-ret (#179383)Anshul Nigham1-3/+3
generated by cgit v1.1 at 2026-02-03 20:31:56 +0000