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2026-02-12[WebAssembly] Error on Wasm SjLj if +exception-handling is missing (#181070)HEADmainHeejin Ahn1-0/+25
2026-02-12[RISCV][NFC] Remove redundant defvar in SiFive7 SchedModel (#181218)Min-Yih Hsu1-1/+0
2026-02-12[SeparateConstOffsetFromGEP] Update splitGEP to handle case where including b...Adel Ejjeh1-7/+20
2026-02-12[MemProf] Emit richer optimization remarks for single-type allocations (#181089)Teresa Johnson1-18/+44
2026-02-12[UTC][VPlan] Use `-vplan-print-after` for VPlan-dump-based tests (#178736)Andrei Elovikov1-1/+4
2026-02-12[HWASan][Fuchsia] Have Fuchsia use a dynamic shadow start (#180881)PiJoules1-1/+1
2026-02-12[SLP]Fix crash with deleted non-copyable node in scheduling copyablesAlexey Bataev1-9/+11
2026-02-12[RISCV] Update sched resources used by XSfvcp instructions (#181206)Min-Yih Hsu1-28/+28
2026-02-12[SLP] Use the correct identity when combining binary opcodes with AND/MUL (#1...Ryan Buchner1-19/+20
2026-02-12[AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe (#177334)Jonathan Thackray2-2/+5
2026-02-12[AsmParserContext] Fix regression after #174566 (#180068)Bertik231-13/+15
2026-02-13[InstructionSimplify] Extend simplifyICmpWithZero to handle equivalent zero R...Kunqiu Chen1-1/+57
2026-02-12[AArch64][llvm] Preserve FP_TO_*_SAT VT operand in SVE scalar-combine (#177333)Jonathan Thackray1-1/+7
2026-02-12[llvm][DebugInfo] Allow anonymous basic types (#180016)Tom Tromey1-1/+0
2026-02-12[DebugInfo] DWARFFormValue use formatv instead of format (#180498)Konrad Kleine1-34/+42
2026-02-12[RISCV] Move NSRL/NSRA isel to tablegen. NFC (#181096)Craig Topper3-34/+22
2026-02-12[VPlan] Explicitly reassociate header mask in logical and (#180898)Luke Lau1-9/+27
2026-02-12Revert "[IndVarSimplify] Add safety check for getTruncateExpr in genLoopLimit...Nikita Popov1-93/+89
2026-02-12[AggressiveInstCombine] Create zext during store merge (#181125)Nikita Popov1-1/+1
2026-02-12[VPlan] Introduce m_c_Logical(And|Or) (#180048)Ramkumar Ramachandra3-6/+35
2026-02-12[NFC][AMDGPU] Remove unused `getLDSSize` (#181133)Juan Manuel Martinez Caamaño1-8/+0
2026-02-12[NFC][AMDGPU] Remove unused/unimplemented `getWavesPerEU` variants (#181131)Juan Manuel Martinez Caamaño2-17/+0
2026-02-12[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)Matthew Devereau2-2/+16
2026-02-12[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)Guy David1-0/+65
2026-02-12[AArch64]Add SCR2_EL3 system register (#180918)CarolineConcatto1-0/+4
2026-02-12[SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)Björn Pettersson3-10/+29
2026-02-12[DAGCombiner] Fix subvector extraction index for big-endian STLF (#180795)陈子昂1-2/+13
2026-02-12[AArch64][ISel] Add clmul to pmullb/t lowering (#180568)Matthew Devereau2-1/+12
2026-02-12[SDAG] Copy flags in convertMask when legalizing vselect/setcc (#180979)David Green1-1/+2
2026-02-12Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)sstipano15-143/+145
2026-02-11[RISCV] Improve 2*XLEN SHL legalization with P extension. (#181056)Craig Topper1-12/+55
2026-02-11[RISCV] Use NSRL/NSRA for legalizing i64 shifts with P extension on RV32. (#1...Craig Topper3-5/+103
2026-02-12[Hexagon] Add support for V128i1/V64i1/V32i1 predicate store/load in HVX (#18...pkarveti2-1/+133
2026-02-11Revert "[MC/DC] Make covmap tolerant of nested Decisions (#125407)" (#181069)gulfemsavrun1-135/+168
2026-02-12[RISCV] Update Andes45 vector fixed-point arithmetic scheduling info (#180451)Jim Lin1-13/+23
2026-02-12[AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert ...Lucas Ramirez2-38/+50
2026-02-11[DTLTO][Windows] Expand short 8.3 form paths in ThinLTO module IDs (#178303)Ben Dunbobbin1-9/+59
2026-02-11[SLP]Add external uses estimations into tree throttlingAlexey Bataev1-26/+111
2026-02-11[SPIRV] Scalarize single-element vectors in type creation (#180735)Dmitry Sidorov1-0/+6
2026-02-11[LV] Don't scalarize loads that need predication in legacy CM.Florian Hahn1-3/+3
2026-02-11[DominanceFrontier] Support post-dominators on graphs with single root (#179336)Andrei Elovikov2-3/+0
2026-02-11[NFC] [MemoryTagging] pass AllocaInfo to isStandardLifetime (#180311)Florian Mayer3-12/+9
2026-02-11[AMDGPU][ISel] `setcc` peephole for comparisons with upper 32 bits of a 64-bi...zGoldthorpe1-0/+20
2026-02-11[AMDGPU][GlobalIsel] Add register bank legalization rules for buffer atomic i...Syadus Sefat1-1/+4
2026-02-11[VPlan] Remove VPUnrollPartAccessor from VPReductionPHIRecipe (NFC).Florian Hahn2-3/+1
2026-02-11[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180...Jay Foad1-1/+3
2026-02-11[SLP]Correctly process deleted gathered loads and short treesAlexey Bataev1-0/+18
2026-02-11[clang-sycl-linker][offload] Set TheImageKind based on IsAOTCompileNeeded fla...Yury Plyakhin1-0/+3
2026-02-11[LoopUnrollPass] Indent `LLVM_DEBUG()` messages based on our depth in the `tr...Justin Fargnoli1-38/+50
2026-02-11AMDGPU/GlobalISel: RegBankLegalize for global atomic ordered add (#180829)vangthao951-0/+3
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