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| author | Craig Topper <craig.topper@sifive.com> | 2025-04-04 12:11:26 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2025-04-04 12:49:09 -0700 |
| commit | 9069ba183d0ad56a1e7b9710d9198686bc9b888b (patch) | |
| tree | 1d6697ae994139ea3449e1376ab8d0313fdf85bc /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 6263de90df7f58c8b98475024d5eef102e10a372 (diff) | |
| download | llvm-9069ba183d0ad56a1e7b9710d9198686bc9b888b.zip llvm-9069ba183d0ad56a1e7b9710d9198686bc9b888b.tar.gz llvm-9069ba183d0ad56a1e7b9710d9198686bc9b888b.tar.bz2 | |
[RISCV] Rename Spimm to StackAdj in most places. NFC
Spimm in the spec refers to the 2-bit encoded value. All of the code
uses the 0, 16, 32, or 48 adjustment value.
Also remove the decodeZcmpSpimm as its identical to the default
behavior for no custom DecoderMethod.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 0994901..716299a 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -527,8 +527,8 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, - uint64_t Address, const void *Decoder); +static DecodeStatus decodeZcmpStackAdj(MCInst &Inst, uint32_t Imm, + uint64_t Address, const void *Decoder); static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, @@ -668,12 +668,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, return MCDisassembler::Success; } -static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, - uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::createImm(Imm)); - return MCDisassembler::Success; -} - // Add implied SP operand for C.*SP compressed instructions. The SP operand // isn't explicitly encoded in the instruction. void RISCVDisassembler::addSPOperands(MCInst &MI) const { |