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author | Jim Lin <jim@andestech.com> | 2025-06-18 09:17:46 +0800 |
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committer | GitHub <noreply@github.com> | 2025-06-18 09:17:46 +0800 |
commit | 8ddada41df0488358373cff1d31a47e5ef4961e0 (patch) | |
tree | 0d7cd7d8a3c4057c70b5619f5b8fd4ce00745845 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
parent | 9265b1f0cff74c929214efb64f41183299f31772 (diff) | |
download | llvm-8ddada41df0488358373cff1d31a47e5ef4961e0.zip llvm-8ddada41df0488358373cff1d31a47e5ef4961e0.tar.gz llvm-8ddada41df0488358373cff1d31a47e5ef4961e0.tar.bz2 |
[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index cbab081..27e04c0 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -774,8 +774,8 @@ static constexpr FeatureBitset XTHeadGroup = { RISCV::FeatureVendorXTHeadVdot}; static constexpr FeatureBitset XAndesGroup = { - RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVPackFPH, - RISCV::FeatureVendorXAndesVDot}; + RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt, + RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; static constexpr DecoderListEntry DecoderList32[]{ // Vendor Extensions |