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| author | Paul Bowen-Huggett <paulhuggett@mac.com> | 2025-03-31 17:51:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-31 08:51:34 -0700 |
| commit | ea06f7f96fb1ce5a77439cf1a26f97c2f2488648 (patch) | |
| tree | f4af4d14001cd65acf085fe6f94afc11f8036a73 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 799e9053641a6478d3144866a97737b37b87c260 (diff) | |
| download | llvm-ea06f7f96fb1ce5a77439cf1a26f97c2f2488648.zip llvm-ea06f7f96fb1ce5a77439cf1a26f97c2f2488648.tar.gz llvm-ea06f7f96fb1ce5a77439cf1a26f97c2f2488648.tar.bz2 | |
[RISCV] For RV32C, disassembly of c.slli should fail when immediate > 31 (#133713)
Fixes #133712.
The change causes `c.slli` instructions whose immediate has bit 5 set to
be rejected when disassembling RV32C. Added a test to exhaustively cover
c.slli for 32 bit targets. A minor tweak to make the debug output a
little more readable.
The spec. (20240411) says:
> For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are
designated for custom extensions. For RV32C and RV64C, the shift amount
must be non-zero; the code points with shamt=0 are HINTs. For all base
ISAs, the code points with rd=x0 are HINTs, except those with shamt[5]=1
in RV32C.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index b46b72b..b22a4a7 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -558,8 +558,12 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, const MCDisassembler *Decoder) { Inst.addOperand(MCOperand::createReg(RISCV::X0)); Inst.addOperand(Inst.getOperand(0)); - uint32_t UImm6 = - fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + + uint32_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5; + // On RV32C, uimm[5]=1 is reserved for custom extensions. + if (UImm6 != 0 && Decoder->getSubtargetInfo().hasFeature(RISCV::Feature32Bit)) + return MCDisassembler::Fail; + UImm6 |= fieldFromInstruction(Insn, 2, 5); [[maybe_unused]] DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); @@ -784,7 +788,7 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size, if (!Entry.haveContainedFeatures(STI.getFeatureBits())) continue; - LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << "table:\n"); + LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n"); DecodeStatus Result = decodeInstruction(Entry.Table, MI, Insn, Address, this, STI); if (Result == MCDisassembler::Fail) @@ -820,7 +824,7 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size, if (!Entry.haveContainedFeatures(STI.getFeatureBits())) continue; - LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << "table:\n"); + LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n"); DecodeStatus Result = decodeInstruction(Entry.Table, MI, Insn, Address, this, STI); if (Result == MCDisassembler::Fail) |