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AgeCommit message (Expand)AuthorFilesLines
11 days[WebAssembly] Error on Wasm SjLj if +exception-handling is missing (#181070)HEADmainHeejin Ahn1-0/+25
11 days[RISCV][NFC] Remove redundant defvar in SiFive7 SchedModel (#181218)Min-Yih Hsu1-1/+0
12 days[RISCV] Update sched resources used by XSfvcp instructions (#181206)Min-Yih Hsu1-28/+28
12 days[AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe (#177334)Jonathan Thackray2-2/+5
12 days[AArch64][llvm] Preserve FP_TO_*_SAT VT operand in SVE scalar-combine (#177333)Jonathan Thackray1-1/+7
12 days[RISCV] Move NSRL/NSRA isel to tablegen. NFC (#181096)Craig Topper3-34/+22
12 days[NFC][AMDGPU] Remove unused `getLDSSize` (#181133)Juan Manuel Martinez Caamaño1-8/+0
12 days[NFC][AMDGPU] Remove unused/unimplemented `getWavesPerEU` variants (#181131)Juan Manuel Martinez Caamaño2-17/+0
12 days[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)Matthew Devereau2-2/+16
12 days[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)Guy David1-0/+65
12 days[AArch64]Add SCR2_EL3 system register (#180918)CarolineConcatto1-0/+4
12 days[AArch64][ISel] Add clmul to pmullb/t lowering (#180568)Matthew Devereau2-1/+12
12 daysReapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)sstipano13-140/+142
12 days[RISCV] Improve 2*XLEN SHL legalization with P extension. (#181056)Craig Topper1-12/+55
12 days[RISCV] Use NSRL/NSRA for legalizing i64 shifts with P extension on RV32. (#1...Craig Topper3-5/+103
12 days[Hexagon] Add support for V128i1/V64i1/V32i1 predicate store/load in HVX (#18...pkarveti2-1/+133
12 days[RISCV] Update Andes45 vector fixed-point arithmetic scheduling info (#180451)Jim Lin1-13/+23
12 days[AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert ...Lucas Ramirez2-38/+50
12 days[SPIRV] Scalarize single-element vectors in type creation (#180735)Dmitry Sidorov1-0/+6
13 days[NFC] [MemoryTagging] pass AllocaInfo to isStandardLifetime (#180311)Florian Mayer1-2/+1
13 days[AMDGPU][ISel] `setcc` peephole for comparisons with upper 32 bits of a 64-bi...zGoldthorpe1-0/+20
13 days[AMDGPU][GlobalIsel] Add register bank legalization rules for buffer atomic i...Syadus Sefat1-1/+4
13 days[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180...Jay Foad1-1/+3
13 daysAMDGPU/GlobalISel: RegBankLegalize for global atomic ordered add (#180829)vangthao951-0/+3
13 days[X86] Move getTargetVShift helpers earlier in the source file. NFC. (#180972)Simon Pilgrim1-168/+170
13 days[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)vangthao951-0/+5
13 days[RISCV] improve `musttail` support (#170547)Folkert de Vries2-40/+94
13 days[AArch64] Lower factor-of-2 interleaved stores to STNP (#177938)Tomer Shafir3-4/+63
13 days[SPIRV] Replace `SPIRVType` with `SPIRVTypeInst` as much as we can (#180721)Juan Manuel Martinez Caamaño15-954/+989
13 days[SPIRV] Add a `SPIRVTypeInst` type with some guardrails (#179947)Juan Manuel Martinez Caamaño2-5/+63
13 days[AArch64] Avoid selecting XAR for reverse operations. (#178706)Ricardo Jesus1-0/+100
13 days[RISCV][CodeGen] Combine vwaddu+vabd(u) to vwabda(u)Pengcheng Wang3-3/+77
13 days[RISCV] Add sp register as implicit/implicit-def register to save/restore cal...Jim Lin1-2/+5
13 days[RISCV] Remove explicitly adding spilled registers as liveins. (#180483)Jim Lin1-5/+2
13 days[RISCV] Remove vp.reverse mask check in performVP_REVERSECombine (#180724)Luke Lau1-4/+0
13 days[RISCV] Relax reversed mask's mask requirement in reverse to strided load/sto...Luke Lau1-4/+2
13 days[Mips] Fix cttz.i32 fails to lower on mips16 (#179633)yingopq1-2/+4
13 days[PowerPC] Require PPC32 for 32-bit addc/adde/subc/sube (#179186)Nikita Popov1-10/+17
13 days[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)Sameer Sahasrabuddhe4-14/+300
13 days[NewPM] Port x86-insert-x87-wait (#180128)Kyungtak Woo6-14/+31
13 days[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)Sameer Sahasrabuddhe9-37/+115
13 days[IROutliner] Add TTI Hook for Propagating Attributes (#153985)Sam Elliott2-0/+16
13 days[NewPM] Port x86-winehstate (#180687)Anshul Nigham5-49/+95
13 days[X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (#180472)woruyu1-3/+11
13 days[AMDGPU] Fix LDS address correction in promoteConstantOffsetToImm for async s...Alexander Weinrauch1-8/+14
13 days[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#...Craig Topper3-8/+88
13 days[SPIRV] Legalize extended integers for compare instructions. (#180254)Faijul Amin1-0/+4
13 days[RISCV] Use ADDD for GPR Pair Move with P (#180671)Sam Elliott1-7/+17
14 days[RISCV] Refactor the MC layer SiFive VCIX classes. (#180433)Craig Topper1-118/+138
14 days[RISCV] Add (BSETI x0, 11) to isLoadImm for optimizeCondBranch (#180820)Craig Topper1-3/+11
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