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2025-12-09AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)HEADmainanjenner7-78/+19
2025-12-09[RISCV] Fix formatting in RISCVInstrInfoXSf.td. NFC (#171500)Craig Topper1-1/+1
2025-12-09[AArch64] recognise trn1/trn2 with flipped operands (#169858)Philip Ginsbach-Chen3-25/+50
2025-12-09[AMDGPU] Scavenge a VGPR to eliminate a frame index (#166979)Anshil Gandhi1-3/+29
2025-12-09[X86] fix typo: `MCVTTP2SIS` -> `MCVTTP2UIS` (#171229)Folkert de Vries1-1/+1
2025-12-09[ADT] BitVector: give `subsetOf(RHS)` name to `!test(RHS)` (NFC) (#170875)Anatoly Trosinenko2-4/+2
2025-12-09[SPIRV] Start adding support for `int128` (#170798)Alex Voicu6-13/+59
2025-12-09[NVPTX] Add IR pass for FMA transformation in the llc pipeline (#154735)Rajat Bajpai5-0/+185
2025-12-09[RISCV] Use VM and VMNoV0 for "vr" and "vd" inline asm constraints with mask ...Craig Topper1-15/+17
2025-12-09[RISCV] Add VMNoV0 register class with only the VMaskVTs. (#171231)Craig Topper1-0/+1
2025-12-09[Hexagon] Use getSigned() for signed valueNikita Popov1-1/+1
2025-12-09[ThumbRegisterInfo] Use getSigned() for constant pool loadsNikita Popov1-4/+4
2025-12-09[X86] Use getSigned() for segment offsetNikita Popov1-1/+1
2025-12-09[Hexagon] Simplify creation of splat value (NFC)Nikita Popov1-5/+3
2025-12-09[Hexagon] Avoid unnecessary by reference passing (NFC)Nikita Popov1-6/+5
2025-12-09[Hexagon] Remove unnecessarily complicated helpers (NFC)Nikita Popov1-43/+12
2025-12-09[AArch64] Make the list of LSE supported operations explicit (#171126)David Green1-5/+19
2025-12-09Revert "[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)"pvanhout1-310/+281
2025-12-09[AArch64]SIMD fpcvt codegen for rounding nodes (#165546)Lukacma1-0/+43
2025-12-09[FMV][AArch64] Allow user to override version priority. (#150267)Alexandros Lamprineas3-3/+26
2025-12-09[NFC][AMDGPU] Remove unused TableGen generated enum (#171170)Mirko BrkuĊĦanin1-6/+0
2025-12-09[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)Pierre van Houtryve1-281/+310
2025-12-09[AArch64] Add intrinsics support for multi-vector FMUL (#163397)Lukacma1-4/+20
2025-12-09[AArch64][GlobalISel] Added support for neon left shift intrinsics on single-...Joshua Rodriguez1-0/+8
2025-12-09[llvm] Use ConstantInt::getAllOnesValue()Nikita Popov4-7/+9
2025-12-09[SystemZ] Improve CCMask optimization (#171137)Dominik Steenken1-1/+13
2025-12-09[AArch64] Run optimizeTerminators earlier too. (#170907)David Green4-46/+55
2025-12-09Revert "[Mips] Support "$sp" named register (#136821)"YunQiang Su2-92/+12
2025-12-09[X86] LowerAsmOperandForConstraint - ensure we treat L constraint immediates ...Simon Pilgrim1-6/+9
2025-12-09[AMDGPU][NPM] Enable SIModeRegister and SIInsertHardclauses passes (#168831)Vikram Hegde1-4/+3
2025-12-09[Mips] Support "$sp" named register (#136821)yingopq2-12/+92
2025-12-09[Clang] Use DataLayout from TargetParser (#171135)Nikita Popov1-4/+3
2025-12-09[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)Luke Lau3-79/+12
2025-12-09[RISCV] Don't unroll vectorized loops with vector operands (#171089)Pengcheng Wang1-1/+4
2025-12-08[AArch64] Fix missing register definitions in homogeneous epilog lowering (#1...Zhaoxuan Jiang1-10/+17
2025-12-09[AMDGPU][NFC] cleanup whitespace in debug log of SIInsertWaitcntsSameer Sahasrabuddhe1-13/+13
2025-12-09[AMDGPU][NFC] fix function names in debug log for SIInsertWaitcntsSameer Sahasrabuddhe1-4/+4
2025-12-08[NVPTX] Fix lit test issue from used_bytes_mask (#171220)Drew Kersnar2-4/+14
2025-12-09[PowerPC] Use the same lowering rule for vector rounding instructions (#166307)paperchalice1-2/+2
2025-12-09[AArch64] Treat NOP as a separate instruction. (#170968)Harald van Dijk4-14/+15
2025-12-08AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)Matt Arsenault1-0/+1
2025-12-08[RISCV] Remove unnecesary override of getVectorTypeBreakdownForCallingConv. N...Craig Topper2-18/+1
2025-12-08[X86][GlobalISel] Set Dst register correctly when narrowing G_ICMP (#169947)Evgenii Kudriashov1-0/+1
2025-12-08[AMDGPU] Fix a crash when a bool variable is used in inline asm (#171004)Shilei Tian1-0/+4
2025-12-08Fix VarArgs FixedStack object on AIX. (#170240)Sean Fertile1-8/+28
2025-12-08[AArch64] Use sve instructions for fixed-width smulh/umulh. (#166168)David Green1-7/+4
2025-12-08cmse: emit `__acle_se_` symbol for aliases to entry functions (#162109)Folkert de Vries2-0/+32
2025-12-08HexagonGenWideningVecInstr.cpp - fix MSVC "result of 32-bit shift implicitly ...Simon Pilgrim1-1/+1
2025-12-08Fix [PowerPC] llc crashed at -O1/O2/O3: Assertion `isImm() && "Wrong MachineO...zhijian lin1-9/+37
2025-12-08[X86] Handle X86ISD::EXPAND/COMPRESS nodes as target shuffles (#171119)Simon Pilgrim1-0/+46
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