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AgeCommit message (Expand)AuthorFilesLines
7 hours[MTE][Darwin] This patch extends support for the stack frame history buffer t...Usama Hameed1-6/+18
7 hours[AMDGPU][SIInsertWaitcnts] Cleanup: Remove WaitEventMaskForInst member variab...vporpo1-12/+10
8 hours[EarlyIfConversion] Add analysis for data-dependent conditional branches(#174...Jonathan Cohen1-31/+59
9 hours[RISCV] Update P extension to 019. (#178031)Craig Topper2-3/+3
10 hours[X86] LowerBUILD_VECTORvXbf16 - pull out repeated MVT::f16/bf16 selection. NF...Simon Pilgrim1-4/+3
11 hoursAMDGPU: Perform zero/any extend combine into permute (#177370)macurtis-amd2-6/+47
12 hours[AArch64] Remove dead code emission in Pointer Authentication (#175989)Victor Campos1-2/+0
12 hours[AArch64] Refactor PACM emission in Pointer Authentication (NFC) (#175937)Victor Campos1-27/+14
12 hours[LV] Add support for llvm.vector.partial.reduce.fadd (#163975)Damian Heaton6-8/+39
13 hours[AArch64][GlobalISel] Add support for scalar variants of neon right shifts (#...Joshua Rodriguez1-6/+6
13 hours[X86] vectorizeExtractedCast - don't assume vector source type is simple (#17...Simon Pilgrim1-2/+3
14 hours[AMDGPU] Fix buggy insertion of DEALLOC_VGPRS message (#178401)Jay Foad1-20/+18
16 hours[WebAssembly] Fix crash in ReplaceNodeResults for ANY_EXTEND_VECTOR_INREG (#1...hanbeom1-0/+1
16 hours[CostModel][X86] reduce_add(vXi1) will lower as a scalar ctpop (#178400)Simon Pilgrim1-0/+11
17 hours[AMDGPU] Skip printf runtime binding if function signature is unexpected (#17...Steffen Larsen1-0/+11
17 hours[AMDGPU] Fix legacy index in fmed3 optimization (#177426)Steffen Larsen1-1/+1
17 hours[X86] X86FixupInstTunings - attempt to convert VPERMQri to VINSERTI128rri (#1...Julian Pokrovsky1-1/+41
18 hours[AMDGPU] Use FPImmLeaf for float constants, fix build_vector patterns (#178018)Mirko BrkuĊĦanin3-28/+14
18 hours[SystemZ] Enable -fpatchable-function-entry=M,N (#178191)Dominik Steenken3-0/+28
18 hours[Mips] Add r5900 (PlayStation 2 Emotion Engine) CPU support (#176666)Rick Gaiser11-102/+279
18 hours[WebAssembly] Zero and NaN checks for min/max (#177968)Sam Parker3-10/+63
20 hours[RISCV] Remove unnecessary 'let' from VFWMACCBF16_V. NFC (#178367)Craig Topper1-2/+1
21 hours[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)Craig Topper7-76/+85
21 hours[RISCV] Hoist a duplicate setOperationAction to a common place. NFC (#178364)Craig Topper1-4/+2
22 hours[RISCV] Make sure Zvk* and Zvb* predicates are always paired with a GetVTypeP...Craig Topper2-91/+101
24 hours[RISCV] Add missing HasStdExtZvkb Predicate to some of the vector rotate patt...Craig Topper3-12/+15
24 hours[RISCV] Make RVInstIVI_VROR inherit from RVInstVBase. NFC (#178293)Craig Topper1-11/+3
26 hoursRevert "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#1...Akshay Deodhar2-163/+95
28 hours[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)Akshay Deodhar2-95/+163
29 hours[RISCV] Correct the Predicates for Zvqdotq patterns. NFC (#178295)Craig Topper2-18/+20
30 hours[AArch64] Add vector floating-point round+convert patterns (#177801)valadaptive1-0/+51
30 hours[RISCV] Rename Tenstorrent Ascalon D8 to Ascalon X (#178199)Ramkumar Ramachandra3-36/+36
31 hours[AMDGPU] revertScheduling must behave the same with or without debug (#177483)LU-JOHN1-2/+9
31 hours[AArch64] Fuse froundeven+convert into single instruction (#177800)valadaptive1-8/+10
32 hours[RISCV] Remove RVInstV2. NFC (#177901)Craig Topper2-15/+14
32 hours[AArch64] Align nontemporal store/load little-endian checks (#177468)Tomer Shafir3-8/+43
32 hours[AArch64] Add missing GlobalISel patterns to round+convert multiclass (#177799)valadaptive1-0/+15
32 hours[RISCV] Replace VPatBinaryV_VX_VROTATE with VPatBinaryV_VX. NFC (#178254)Craig Topper1-9/+2
32 hours[RISCV] Set the reciprocal throughtput cost for division to TTI::TCC_Expensiv...Ryan Buchner1-2/+20
33 hours[MIPS][ISel] Fix musttail (#161860)Djordje Todorovic2-24/+36
34 hours[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ATOMIC_CMPXCHG (#178066)vangthao953-3/+46
35 hours[TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982)Florian Hahn21-149/+177
36 hours[RISCV] Remove VL from VMV_X_S/VFMV_F_S implicit uses in MC layer. (#178043)Craig Topper1-2/+6
36 hours[regalloc][LiveRegMatrix][AMDGPU] Fix LiveInterval dangling pointers in LiveR...Valery Pykhtin1-2/+4
37 hours[PowerPC] Fix XXPERMDI peephole and ISEL LiveVariables bugs (#172122)Maryam Moghadas3-4/+17
37 hours[AMDGPU] Add SOP1 support for gfx13 (#177618)Mariusz Sikora2-108/+158
38 hours[perf] Replace copy-assign by move-assign in llvm/lib/Target/* (#178179)serge-sans-paille1-1/+1
39 hours[AMDGPU] Add VOP1 support for gfx13 (#177603)Mariusz Sikora4-154/+226
44 hours[RISCV] Fix VRGATHER_V*_VL operands docs. NFC (#178124)Luke Lau1-1/+1
44 hours[RISCV] Support select optimizationPengcheng Wang4-0/+40
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