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9 hours[llvm][OpenMP] Allow Chunk Size on SIMD Guided (#178853)HEADmainJack Styles1-1/+1
10 hours[WebAssembly] Combine shuffle and signed extend to extend_high (#179166)hanbeom2-3/+45
10 hours[HLSL][DXIL][SPIRV] WavePrefixSum intrinsic support (#167946)Kai9-0/+277
10 hours[VPlan] Sink recipes from the vector loop region in licm. (#168031)Mel Chen51-432/+506
10 hoursAttributor: Add denormal-fp-math to attributor-light (#79576)Matt Arsenault2-1/+3
11 hours[RISCV] Pass EEW instead of log2(EEW) to RISCVVXMemOpMC. NFC (#179379)Craig Topper1-10/+10
11 hours[RISCV] Sink conversion from nfields/lmul to nf down one level in RISCVInstrI...Craig Topper1-57/+75
11 hours[AMDGPU] Add SOPK, SOPC and SOPP encoding support for gfx13 (#179179)Mariusz Sikora7-261/+3341
11 hours[RISCV] Default all ISD opcodes to Expand for P extension. (#179396)Craig Topper1-5/+15
12 hours[NVPTX] Print PM Event Mask value as unsigned integer. (#178891)Kirill Vedernikov4-3/+38
12 hours[RISCV] Rename VUnitStrideLoadMask->VUnitStrideMaskLoad. NFC (#179360)Craig Topper3-10/+10
12 hours[RISCV] Rename nf->nfields in MC layer. NFC (#179365)Craig Topper2-124/+120
12 hours[RISCV] Add common base classes for loads/stores in RISCVInstrFormatsV.td. NF...Craig Topper1-68/+28
13 hours[NewPM] Fix callsite for x86-lvi-ret (#179383)Anshul Nigham2-5/+7
15 hours[SPIR-V] Fix FmaKHR CapabilityOperand and Op (#179174)Wenju He2-2/+2
16 hoursRevert "[BasicBlockUtils] Fix dominator tree update for entry block in splitB...Mingjie Xu2-44/+44
16 hours[gn build] Port 5cc4b05380aeLLVM GN Syncbot1-0/+1
16 hours[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)Carl Ritson10-105/+371
17 hours[CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (N...Nicolai Hähnle22-275/+411
17 hours[BasicBlockUtils] Fix dominator tree update for entry block in splitBlockBefo...Mingjie Xu2-44/+44
18 hours[InstCombine] Preserve fdiv metadata on fneg folds (#179157)Wenju He2-4/+44
18 hours[gn build] Port 9d5a42c8411b2Peter Collingbourne1-1/+12
18 hours[gn build] Port 7b6f1235b9353Peter Collingbourne1-0/+1
18 hoursgn build: Port 39413af931a7Peter Collingbourne1-0/+4
19 hours[VPlan] Improve code around ArrayRef construction (NFC) (#179191)Ramkumar Ramachandra1-25/+20
20 hours[Matrix] Add test where pointer phi currently blocks tiling.Florian Hahn1-0/+49
20 hoursRevert "[AutoUpgrade] Prevent deletion of call if uses still exist (#177606)"...Stefan Weigl-Bosker3-58/+25
20 hours[RISC-V][Mach-O] Add codegen support for Mach-O object format. (#178263)Francesco Petrogalli4-1/+110
20 hours[CodeGen] Add getTgtMemIntrinsic overload for multiple memory operands (NFC) ...Nicolai Hähnle10-125/+251
21 hours[AMDGPU][SIInsertWaitcnts][NFC] Replace Wait.combined() with simple assignmen...vporpo1-1/+1
21 hours[perf] Replace copy-assign by move-assign in llvm/lib/Analysis/* (#178169)serge-sans-paille3-7/+6
21 hours[AutoUpgrade] Prevent deletion of call if uses still exist (#177606)Kshitij Paranjape3-25/+58
22 hours[RISCV] Split RISCVLSUMOP tablegen class for type safety. NFCCraig Topper1-10/+14
23 hours[AArch64] Move the existing fcvt fixed point selection to tblgen. (#178603)David Green4-97/+135
23 hours[RISCV] Fix register names for CM_MVSA01/QC_CM_MVSA01 check in RISCVAsmParser...Craig Topper1-3/+3
23 hoursValueTracking: Move powi logic to KnownFPClass (#179301)Matt Arsenault4-16/+34
23 hours[SLP] Avoid adding duplicate VFs into vectorizeStores()::CandidateVFs (#179296)Ryan Buchner1-8/+6
24 hours[Github] Fully remove use of login_or_token (#179258)Aiden Grossman4-14/+22
24 hoursValueTracking: Move ldexp KnownFPClass handling to support (#179235)Matt Arsenault3-48/+63
24 hours[SLP][NFC]Add a case for missed shl-to-add transformation, NFCAlexey Bataev1-0/+76
24 hours[NFC][TableGen] Adopt `IfDefEmitter` in `RegBankEmitter` (#179014)Rahul Joshi1-58/+51
24 hoursInstCombine: Fix SimplifyDemandedFPClass bug with known-snan sources (#179244)Matt Arsenault14-33/+76
25 hoursRevert "[VectorCombine] Trim low end of loads used in shufflevector rebroadca...Hans Wennborg2-71/+31
25 hoursInstCombine: Stop using nsz in multi-use min/max fold (#176579)Matt Arsenault5-11/+12
25 hoursValueTracking: Use computeKnownBits for ldexp integer handling (#179234)Matt Arsenault2-9/+7
25 hoursFix grammar in comments (#179269)Kunal1-1/+1
25 hours[NFC][GlobalISel] Expose `CallLowering::buildCopyFromRegs` and `CallLowering:...Demetrius Kanios2-15/+28
25 hours[LoopUnroll] Remove preceding whitespace in loop peeling optimization remark ...Justin Fargnoli2-6/+6
25 hours[CostModel][X86] clmul.ll - add i16 and 128/256/512-bit vector cost tests (#1...Simon Pilgrim1-1/+79
25 hoursInstCombine: Add baseline tests for broken snan handling (#179243)Matt Arsenault20-2/+579
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