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3 hours[TargetParser][cmake] Recurse for TableGen deps (#177274)HEADmainBrendan Dahl1-1/+1
3 hours[PowerPC] Remove NoInfsFPMath uses (#163029)paperchalice5-1131/+647
4 hoursReland "[DebugMetadata][DwarfDebug] Support function-local types in lexical b...Vladislav Dzhidzhoev26-154/+1583
4 hours[X86] Add test coverage for #179008 (#179562)Simon Pilgrim1-0/+35
5 hours[RISCV] Sink some encoding related lets into class/def bodies. NFC (#179544)Craig Topper1-28/+40
5 hoursReapply "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morp...Craig Topper6-20/+91
5 hours[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)Min-Yih Hsu56-1218/+1232
5 hours[BPF] Replace copy-assign by move-assign in llvm/lib/Target/BPF/ (#179462)serge-sans-paille2-2/+2
6 hours[ArgPromotion] Add DW_CC_nocall to DISubprogram (#178973)yonghong-song2-1/+27
6 hoursRevert "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morph...Craig Topper6-91/+20
6 hours[gn] port e1f69ee8e847Nico Weber1-0/+3
6 hours[NFC][TableGen] Adopt IfDefEmitter in TargetLibraryInfoEmitter (#179388)Rahul Joshi2-41/+36
6 hours[NFC][TableGen] Adopt CodeGenHelpers in X86MnemonicEmitter (#179324)Rahul Joshi1-24/+24
6 hours[NFC][TableGen] Adopt CodeGenHelpers in RegInfoEmitter (#179017)Rahul Joshi4-98/+84
6 hours[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo i...Craig Topper6-20/+91
6 hours[VPlan] Refine exit select check in transformtoPartialReduction.Florian Hahn3-6/+68
7 hours[VPlan] Generalize `VPAllSuccessorsIterator` to support predecessors (#178724)Andrei Elovikov2-64/+137
8 hours[GOFF] Add emission of debug sections (#178677)Kai Nacke2-0/+92
8 hours[llvm][AsmPrinter] Call graph section Flag field enum (#176309)Prabhu Rajasekaran2-11/+14
8 hours[AIX] Implement the ifunc attribute. (#153049)Wael Yehia21-36/+857
8 hours[llvm][RISCV] precommit test update via UTC (#179508)Paul Kirth1-71/+107
9 hours[NFC][TableGen] Adopt CodeGenHelpers in IntrinsicEmitter (#179310)Rahul Joshi4-74/+40
9 hours[LLVM][Intrinsics] Minor cleanup in getIntrinsicInfoTableEntries (#179317)Rahul Joshi1-4/+7
9 hours[AMDGPU] Clear no convergence flag on operand folding. NFCI (#179438)Stanislav Mekhanoshin1-0/+2
9 hours[SPIR-V] Add lowering for G_FSINCOS (#179053)Dmitry Sidorov4-0/+143
9 hoursReapply "[InstCombine] Always fold alignment assumptions into operand bundles...Nikolas Klauser4-64/+49
9 hoursARM: Avoid using isTarget wrappers around Triple predicates (#179512)Matt Arsenault2-22/+31
9 hours[InstCombine] fold icmp ne (and X, 1), 0 --> trunc X to i1 (#178977)Andreas Jonson21-255/+215
10 hours[X86] mayFoldIntoVector - recognise larger than legal logic ops may fold to v...Simon Pilgrim1-4/+6
10 hours[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp...Syadus Sefat6-12/+449
10 hoursInstCombine: Handle minnum/maxnum in SimplifyDemandedFPClass (#179299)Matt Arsenault4-354/+233
10 hours[InlineCost] Replace getAllocatedType with getAllocationSize (#178355)Jameson Nash1-11/+12
10 hours[AMDGPU][GlobalISel] Add tbuffer store d16 RegBankLegalize rule (#179411)vangthao955-10/+11
10 hours[X86] Restrict offset folding into address mode in 16-bit mode (#179399)Fangrui Song3-0/+50
11 hours[CodeGen][AArch64] ptrauth intrinsic to safely construct relative ptr (#142047)Abhay Kanhere7-18/+758
11 hours[AMDGPU][Scheduler] Fix incorrect region index in EXPENSIVE_CHECKS (#179461)Lucas Ramirez1-31/+28
11 hoursAMDGPU/GlobalISel: add mir test for sgpr s16 unmerge (#179440)Petar Avramovic1-0/+65
11 hours[InstCombine] Fold select of intrinsic into intrinsic of select (#178002)Gauravsingh Sisodia3-0/+202
11 hours[InstCombine] Extend canonicalization of addition to positive numbers (#179343)SiliconA-Z2-22/+201
12 hours[OpenMPOpt] avoid OOB array write (#178686)Jameson Nash1-2/+5
12 hours[RISCV] Wrap some long lines in RISCVInstrInfoV.td. NFCCraig Topper1-7/+10
12 hours[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)Kito Cheng17-55/+162
12 hours[LegalizeTypes] Don't promote operands to VP extends (#179475)Luke Lau27-162/+114
12 hours[Hexagon] Fix a bug in setcc isnan lit test for f16 (#179338)Fateme Hosseini1-3/+5
12 hours[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVIns...Craig Topper2-55/+46
13 hoursReland "[BasicBlockUtils] Fix dominator tree update for entry block in splitB...Mingjie Xu3-45/+46
13 hours[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)serge-sans-paille8-13/+13
13 hours[AArch64][PAC] Mark $Scratch operand of AUTxMxN as earlyclobber (#173999)Anatoly Trosinenko3-5/+96
13 hours[SLP]Disable modeling disjoint reduction or as bitcast for big endianAlexey Bataev2-1/+262
14 hours[AMDGPU] Implement llvm.sponentry (#176357)Diana Picus12-10/+565
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