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104 min.Reapply "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morp...HEADmainCraig Topper6-20/+91
113 min.[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)Min-Yih Hsu56-1218/+1232
116 min.[BPF] Replace copy-assign by move-assign in llvm/lib/Target/BPF/ (#179462)serge-sans-paille2-2/+2
2 hours[ArgPromotion] Add DW_CC_nocall to DISubprogram (#178973)yonghong-song2-1/+27
2 hoursRevert "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/Morph...Craig Topper6-91/+20
3 hours[gn] port e1f69ee8e847Nico Weber1-0/+3
3 hours[NFC][TableGen] Adopt IfDefEmitter in TargetLibraryInfoEmitter (#179388)Rahul Joshi2-41/+36
3 hours[NFC][TableGen] Adopt CodeGenHelpers in X86MnemonicEmitter (#179324)Rahul Joshi1-24/+24
3 hours[NFC][TableGen] Adopt CodeGenHelpers in RegInfoEmitter (#179017)Rahul Joshi4-98/+84
3 hours[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo i...Craig Topper6-20/+91
3 hours[VPlan] Refine exit select check in transformtoPartialReduction.Florian Hahn3-6/+68
3 hours[VPlan] Generalize `VPAllSuccessorsIterator` to support predecessors (#178724)Andrei Elovikov2-64/+137
4 hours[GOFF] Add emission of debug sections (#178677)Kai Nacke2-0/+92
5 hours[llvm][AsmPrinter] Call graph section Flag field enum (#176309)Prabhu Rajasekaran2-11/+14
5 hours[AIX] Implement the ifunc attribute. (#153049)Wael Yehia21-36/+857
5 hours[llvm][RISCV] precommit test update via UTC (#179508)Paul Kirth1-71/+107
5 hours[NFC][TableGen] Adopt CodeGenHelpers in IntrinsicEmitter (#179310)Rahul Joshi4-74/+40
5 hours[LLVM][Intrinsics] Minor cleanup in getIntrinsicInfoTableEntries (#179317)Rahul Joshi1-4/+7
5 hours[AMDGPU] Clear no convergence flag on operand folding. NFCI (#179438)Stanislav Mekhanoshin1-0/+2
5 hours[SPIR-V] Add lowering for G_FSINCOS (#179053)Dmitry Sidorov4-0/+143
6 hoursReapply "[InstCombine] Always fold alignment assumptions into operand bundles...Nikolas Klauser4-64/+49
6 hoursARM: Avoid using isTarget wrappers around Triple predicates (#179512)Matt Arsenault2-22/+31
6 hours[InstCombine] fold icmp ne (and X, 1), 0 --> trunc X to i1 (#178977)Andreas Jonson21-255/+215
6 hours[X86] mayFoldIntoVector - recognise larger than legal logic ops may fold to v...Simon Pilgrim1-4/+6
6 hours[AMDGPU][GlobalIsel] Add register bank legalization rules for fptoi and itofp...Syadus Sefat6-12/+449
7 hoursInstCombine: Handle minnum/maxnum in SimplifyDemandedFPClass (#179299)Matt Arsenault4-354/+233
7 hours[InlineCost] Replace getAllocatedType with getAllocationSize (#178355)Jameson Nash1-11/+12
7 hours[AMDGPU][GlobalISel] Add tbuffer store d16 RegBankLegalize rule (#179411)vangthao955-10/+11
7 hours[X86] Restrict offset folding into address mode in 16-bit mode (#179399)Fangrui Song3-0/+50
7 hours[CodeGen][AArch64] ptrauth intrinsic to safely construct relative ptr (#142047)Abhay Kanhere7-18/+758
7 hours[AMDGPU][Scheduler] Fix incorrect region index in EXPENSIVE_CHECKS (#179461)Lucas Ramirez1-31/+28
7 hoursAMDGPU/GlobalISel: add mir test for sgpr s16 unmerge (#179440)Petar Avramovic1-0/+65
7 hours[InstCombine] Fold select of intrinsic into intrinsic of select (#178002)Gauravsingh Sisodia3-0/+202
7 hours[InstCombine] Extend canonicalization of addition to positive numbers (#179343)SiliconA-Z2-22/+201
8 hours[OpenMPOpt] avoid OOB array write (#178686)Jameson Nash1-2/+5
8 hours[RISCV] Wrap some long lines in RISCVInstrInfoV.td. NFCCraig Topper1-7/+10
8 hours[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)Kito Cheng17-55/+162
9 hours[LegalizeTypes] Don't promote operands to VP extends (#179475)Luke Lau27-162/+114
9 hours[Hexagon] Fix a bug in setcc isnan lit test for f16 (#179338)Fateme Hosseini1-3/+5
9 hours[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVIns...Craig Topper2-55/+46
9 hoursReland "[BasicBlockUtils] Fix dominator tree update for entry block in splitB...Mingjie Xu3-45/+46
10 hours[perf] Replace copy-assign by move-assign in llvm/lib/Target/AMDGPU/ (#179460)serge-sans-paille8-13/+13
10 hours[AArch64][PAC] Mark $Scratch operand of AUTxMxN as earlyclobber (#173999)Anatoly Trosinenko3-5/+96
10 hours[SLP]Disable modeling disjoint reduction or as bitcast for big endianAlexey Bataev2-1/+262
10 hours[AMDGPU] Implement llvm.sponentry (#176357)Diana Picus12-10/+565
11 hoursReland "[CoroCleanup] Noop coroutine elision for load-and-call pattern (#1791...Weibo He3-48/+129
12 hours[VPlan] Always set flags for overflowing ops etc via VPIRFlags. (#179138)Florian Hahn10-108/+249
12 hours[SLP][NFC]Add another test for shl-to-add transformation, NFCAlexey Bataev1-0/+34
13 hoursRevert "[SeparateConstOffsetFromGEP] Decompose constant xor operand if possib...Eli Friedman3-519/+6
13 hours[AArch64][SME] Limit where SME ABI optimizations apply (#179273)Benjamin Maxwell6-345/+162
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