aboutsummaryrefslogtreecommitdiff
path: root/llvm
AgeCommit message (Expand)AuthorFilesLines
47 min.[llvm-readelf] --unwind: Support DW_EH_PE_sdata8 encoding (#179152)HEADmainFangrui Song3-7/+165
53 min.[AMDGPU][GlobalISel] Add buffer load format D16 RegBankLegalize rules (#179566)vangthao959-24/+31
65 min.Update my email across the project (#179361)Reid Kleckner1-2/+2
70 min.AMDGPU: Implement computeKnownFPClass for llvm.amdgcn.fract (#179134)Matt Arsenault2-0/+83
76 min.AMDGPU: Implement computeKnownFPClass for llvm.amdgcn.trig.preop (#179026)Matt Arsenault2-0/+16
76 min.AMDGPU: Fix incorrect fold of undef for llvm.amdgcn.trig.preop (#179025)Matt Arsenault2-43/+44
82 min.[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas...Akshay Deodhar7-12/+21
85 min.[SystemZ][z/OS] Reverse the order of instructions to save and restore CSRs (#...sujianIBM2-32/+37
111 min.[X86] Fix incorrect SUBREG_TO_REG usage in a MIR test (#179682)Jay Foad1-2/+2
2 hours[SLP][NFC]Add another shl-to-add transformation test, NFCAlexey Bataev1-0/+56
2 hours[X86] Lower i512 ADD/SUB using Kogge-Stone on AVX512 (#174761)Islam Imad3-80/+529
2 hours[SystemZ][z/OS] Set R5 as not restored. (#179666)sujianIBM2-5/+28
2 hours[TableGen] Remove warning IntrinsicsToAttributesMap needs > 16 bits (#179533)Rahul Joshi1-4/+0
2 hours[AMDGPU][True16] t16 pseudo for mubuffer d16 load/store (#178822)Brox Chen33-718/+1222
3 hours[gn build] Port 5cc22a9772c6LLVM GN Syncbot1-0/+1
3 hours[SystemZ][GOFF] Implement lowerConstant (#179394)Tony Tao3-0/+71
4 hours[NFC][LowerMemIntrinsics] Consistent parameter name comments in function call...Fabian Ritter1-53/+53
4 hours[SPIR-V] Fix environment resolution causing legalization crash (#179052)Dmitry Sidorov6-44/+87
4 hoursSPIRVInstructionSelector::selectExtractVal - add missing brackets to assertio...Simon Pilgrim1-3/+2
4 hours[ExpandIRInsts] Freeze value before fptoi expansion (#179659)Nikita Popov4-20/+81
4 hours[perf] Replace copy-assign by move-assign in llvm/lib/Target (#179464)serge-sans-paille2-3/+3
5 hours[AMDGPU] Add machineFunctionInfo to recent MIR tests (#179602)Carl Ritson2-3/+4
6 hours[LowerMemIntrinsics] Optimize memset lowering (#169040)Fabian Ritter18-325/+4898
6 hours[CodeGen] Simplify ExpandPostRA::LowerSubregToReg. NFC. (#179634)Jay Foad1-25/+13
6 hours[X86] Fold EXPAND(X,Y,M) -> SELECT(M,X,Y) when M is a lowest bit mask (#179630)Simon Pilgrim4-7/+16
7 hours[AArch64] Fix a couple of typos (NFC) (#179639)Benjamin Maxwell1-7/+7
7 hours[NFC][LLVM] Make `MachineInstrBuilder::constrainAllUses` return `void` (#179632)Juan Manuel Martinez Caamaño8-627/+615
7 hours[AMDGPU][SIRegisterInfo] Fix maxoffset calculation in buildSpillLoadStore (#1...Abhinav Garg2-1/+36
7 hours[AMDGPU] Add CmpLG and OrN2 operators to LaneMaskConstants (#179493)idubinov1-0/+4
7 hours[X86] computeKnownBitsForTargetNode - extend X86ISD::BZHI handling. Fixes 177...Shamshura Egor2-1/+62
8 hoursAMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize (#179441)Petar Avramovic2-7/+9
8 hours[X86] Fold vgf2p8affineqb XOR with splat constant into immediate (#179103)bala-bhargav3-0/+235
8 hours[HEXAGON] Extend/Truncate the shift amount into i32 (#179499)Abinaya Saravanan2-2/+35
8 hours[AArch64] Add clmul AArch64 lowering tests (#179495)Matthew Devereau3-16/+2084
9 hours[PowerPC] Only set QualName symbol on first section switch (#179253)Nikita Popov2-2/+34
9 hours[X86] Lower CTTZ/CTLZ vXi8 vectors using GF2P8AFFINEQB (#118012)Simon Pilgrim3-496/+208
9 hours[SimpleLoopUnswitch][NFC] move quadratic asserts under EXPENSIVE_CHECKS (#144...jeanPerier1-1/+5
10 hours[NFC][LLVM] Make `constrainSelectedInstRegOperands` return `void` (#179501)Juan Manuel Martinez Caamaño13-221/+243
10 hours[SPIRV] selectDot4AddPacked: add missing PackedVectorFormat4x8Bit optional op...Juan Manuel Martinez Caamaño3-14/+16
11 hours[LegalizeVectorTypes] Don't emit VP_SELECT when widening MLOAD to VP_LOAD (#1...Luke Lau1-3/+6
11 hours[RISCV] Don't emit VP_SETCC in combineVectorSizedSetCCEquality. NFC (#179479)Luke Lau1-2/+1
12 hours[RISCV] Use RVInstVV as the base for CustomSiFiveVMACC. NFC (#179565)Craig Topper1-3/+8
12 hours[perf] Replace extra copy-assign by move-assign in llvm/lib/ (#179465)serge-sans-paille2-4/+2
12 hours[perf] Replace copy-assign by move-assign in llvm/tools/ (#179463)serge-sans-paille1-1/+1
12 hours[RISCV] Add macro fusion support for spacemit-x100 (#178594)Mark Zhuang9-1/+610
12 hours[RISCV] Run VLOptimizer right after ISel (#179377)Min-Yih Hsu79-414/+433
12 hours[InstCombine] Bubble splices of binop operands to their result (#179432)Luke Lau2-0/+172
12 hours[AMDGPU][NPM] Add target-specific register allocation options (#178889)Teja Alaghari3-32/+168
12 hours[RISCV] Enable SelectCompressOpt with HasStdExtZca. (#179601)Craig Topper3-4/+4
13 hours[LLVM] Remove 'libclc' from ALL projects (#179485)Joseph Huber1-2/+2
generated by cgit v1.1 at 2026-02-04 18:13:16 +0000