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2026-02-12[WebAssembly] Error on Wasm SjLj if +exception-handling is missing (#181070)HEADmainHeejin Ahn7-10/+58
2026-02-12[RISCV][NFC] Remove redundant defvar in SiFive7 SchedModel (#181218)Min-Yih Hsu1-1/+0
2026-02-12[SeparateConstOffsetFromGEP] Update splitGEP to handle case where including b...Adel Ejjeh2-7/+108
2026-02-12[MemProf] Emit richer optimization remarks for single-type allocations (#181089)Teresa Johnson2-23/+76
2026-02-12[UTC][VPlan] Use `-vplan-print-after` for VPlan-dump-based tests (#178736)Andrei Elovikov13-143/+124
2026-02-12[HWASan][Fuchsia] Have Fuchsia use a dynamic shadow start (#180881)PiJoules3-12/+12
2026-02-12[SLP]Fix crash with deleted non-copyable node in scheduling copyablesAlexey Bataev5-30/+200
2026-02-12[RISCV] Update sched resources used by XSfvcp instructions (#181206)Min-Yih Hsu2-28/+190
2026-02-12[ADT] Allow member pointers in map_range and map_to_vector (#181154)Jakub Kuderski4-3/+53
2026-02-12[Docs] Improve Target TableGen Docs (#178518)Sam Elliott2-29/+279
2026-02-12[ADT] Add const check to MutableArrayRef constructor (#181190)Dmitrii Makarenko2-1/+6
2026-02-12[SLP] Use the correct identity when combining binary opcodes with AND/MUL (#1...Ryan Buchner5-22/+134
2026-02-12[AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe (#177334)Jonathan Thackray4-1917/+225
2026-02-12[AsmParserContext] Fix regression after #174566 (#180068)Bertik232-13/+27
2026-02-13[InstructionSimplify] Extend simplifyICmpWithZero to handle equivalent zero R...Kunqiu Chen4-15/+279
2026-02-12[AArch64][llvm] Preserve FP_TO_*_SAT VT operand in SVE scalar-combine (#177333)Jonathan Thackray3-1/+3306
2026-02-12In-class initialize DenseMapBase members. (#177168)Matt Davis1-4/+4
2026-02-12[llvm][DebugInfo] Allow anonymous basic types (#180016)Tom Tromey2-1/+23
2026-02-12[llvm-mc-assemble-fuzzer] Fix Triple passing (#181135)Tomer Shafir1-3/+3
2026-02-12[DebugInfo] DWARFFormValue use formatv instead of format (#180498)Konrad Kleine2-34/+65
2026-02-12[RISCV] Move NSRL/NSRA isel to tablegen. NFC (#181096)Craig Topper3-34/+22
2026-02-12[VPlan] Explicitly reassociate header mask in logical and (#180898)Luke Lau6-32/+53
2026-02-12[IR] Change getParamIndexForOptionalMask to assume masked parameter is last (...David Sherwood1-4/+15
2026-02-12[LV] Add LoopVectorize/VPlan subdirectory for VPlan printing tests. (#180611)Florian Hahn38-45/+12
2026-02-12Revert "[IndVarSimplify] Add safety check for getTruncateExpr in genLoopLimit...Nikita Popov2-242/+89
2026-02-12[AggressiveInstCombine] Create zext during store merge (#181125)Nikita Popov2-1/+18
2026-02-12[ReleaseNotes] Create subheader for LLDB/FreeBSD (#181000)Minsoo Choo1-2/+11
2026-02-12[Hexagon] Update maintainers (#177935)Nikita Popov1-3/+8
2026-02-12[VPlan] Introduce m_c_Logical(And|Or) (#180048)Ramkumar Ramachandra4-6/+118
2026-02-12[NFC][AMDGPU] Remove unused `getLDSSize` (#181133)Juan Manuel Martinez Caamaño1-8/+0
2026-02-12[NFC][AMDGPU] Remove unused/unimplemented `getWavesPerEU` variants (#181131)Juan Manuel Martinez Caamaño2-17/+0
2026-02-12[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)Matthew Devereau3-631/+664
2026-02-12[AArch64][GlobalISel] Add some extra sqxtn test coverage. NFCDavid Green2-20/+347
2026-02-12[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)Guy David2-0/+184
2026-02-12[AArch64]Add SCR2_EL3 system register (#180918)CarolineConcatto2-0/+28
2026-02-12[AArch64][GlobalISel] Update and regnerate switch-cases-to-branch-and.ll. NFCDavid Green1-543/+438
2026-02-12[SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)Björn Pettersson17-54/+159
2026-02-12[DAGCombiner] Fix subvector extraction index for big-endian STLF (#180795)陈子昂3-4/+42
2026-02-12[AMDGPU] Add missing assert requirement to unit test (#181102)Lucas Ramirez1-0/+1
2026-02-12[AArch64][ISel] Add clmul to pmullb/t lowering (#180568)Matthew Devereau3-708/+1072
2026-02-12[SDAG] Copy flags in convertMask when legalizing vselect/setcc (#180979)David Green2-97/+14
2026-02-12Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)sstipano23-180/+182
2026-02-11[RISCV] Improve 2*XLEN SHL legalization with P extension. (#181056)Craig Topper3-45/+68
2026-02-11[RISCV] Use NSRL/NSRA for legalizing i64 shifts with P extension on RV32. (#1...Craig Topper4-43/+143
2026-02-12[Hexagon] Add support for V128i1/V64i1/V32i1 predicate store/load in HVX (#18...pkarveti3-1/+222
2026-02-12[NFC][TableGen] Use std::move to avoid copy (#180775)JaydeepChauhan141-1/+1
2026-02-12[llvm-dwp] Adds --prioritize-discard-path to explicitly control dwp overflow ...Liu Ke3-0/+75
2026-02-12[llvm-ir2vec] Adding BB Embeddings Map API to ir2vec python bindings (#180135)Nishant Sachdeva4-5/+97
2026-02-11Revert "[MC/DC] Make covmap tolerant of nested Decisions (#125407)" (#181069)gulfemsavrun2-142/+175
2026-02-12[RISCV] Update Andes45 vector fixed-point arithmetic scheduling info (#180451)Jim Lin4-1044/+1054
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