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97 min.Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180...Justin Fargnoli16-97/+186
2 hours[NFC] Initialize AtomicLoadExtActions array (#180752)JaydeepChauhan141-0/+1
3 hours[AMDGPU][NFC] Use RegisterOperand instead of RegisterClass (#180574)Ryan Mitchell3-101/+101
3 hours[Windows][Support] Add helper to expand short 8.3 form paths (#178480)Ben Dunbobbin3-15/+241
4 hours[VPlan] Fix convertToPhisToBlends folding non poison blend to poison (#180686)Luke Lau2-4/+91
4 hours[LoopVectorizer] Rename variable (NFC). (#180585)Jonas Paulsson1-3/+3
4 hours[VPlan] Add `-vplan-print-after=` option (#178700)Andrei Elovikov3-4/+43
4 hours[LoopVectorizer] Generate test checks (NFC)Nikita Popov1-4/+94
4 hours[NFC][TableGen] Adopt CodeGenHelpers in GobalISel emitters (#180143)Rahul Joshi5-45/+73
4 hours[gn build] Port a56b877056abLLVM GN Syncbot1-0/+1
4 hours[gn build] Port 239876941273LLVM GN Syncbot1-0/+1
4 hours[gn build] Port 1bfa71743b08LLVM GN Syncbot1-0/+1
5 hours[gn] port a29f0dd09680 (llubi)Nico Weber3-0/+25
5 hoursRevert "[SLP]Support for zext i1 %x modeling as select %x, 1, 0"Alexey Bataev3-158/+323
5 hours[X86] SimplifyDemandedVectorEltsForTargetNode - add handling for vpmaddwd/vpm...Simon Pilgrim2-12/+9
5 hours[ConstraintElim] Infer linear constraints from udiv and urem (#180689)Manasij Mukherjee2-0/+386
6 hours[AArch64][GlobalISel] Add test coverage for arm64-neon-2velem-high.ll and mla...David Green2-242/+517
6 hours[SLP]Support for zext i1 %x modeling as select %x, 1, 0Alexey Bataev3-323/+158
6 hours[SCEV] Don't create SCEVPtrToAddr for unstable pointer representations. (#180...Florian Hahn2-8/+15
6 hours[Thumb2] mve-shuffle.ll - add missing check prefix coverage for some fullfp16...Simon Pilgrim1-2/+226
7 hoursRename llvm/test/Transforms/LoopIdiom/Sparc -> /SPARCChristian Sigg2-0/+0
7 hours[X86] Add tests showing failure to reduce the vector width of vpmaddwd/vpmadd...Simon Pilgrim1-0/+71
7 hours[Verifier] Make verifier fail when global variable size exceeds address space...Steffen Larsen5-3/+33
7 hours[X86] Fixed flags issue of onlyZeroFlagUsed (#180405)JaydeepChauhan141-1/+5
8 hours[IVDesc] Add `[[maybe_unused]]` to `NumNonPHIUsers` (NFC) (#180729)Benjamin Maxwell1-1/+1
9 hours[AMDGPU] Add dot4 fp8/bf8 instructions for gfx1170 (#180516)Mirko Brkušanin14-8/+806
9 hours[LV] Handle partial sub-reductions with sub in middle block. (#178919)Sander de Smalen5-51/+174
9 hours[NFC] Modify the comment of LoopRotate param (#180675)Ningning Shi(史宁宁)1-2/+2
9 hours[TySan] Add skeleton for adding interface functions (#170859)Matthew Nagy1-0/+1
9 hours[CoroSplit][DebugInfo] Fix scope of continuation funclets (#180523)Felipe de Azevedo Piovezan2-2/+73
9 hours[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)Anshil Gandhi6-18/+1607
9 hours[SCEV] Add ptrtoaddr tests with external state/unstable addrspaces.Florian Hahn1-1/+76
10 hours[AArch64] Add support for intent to read prefetch intrinsic (#179709)Kerry McLaughlin6-1/+38
10 hoursReland "[LV] Support conditional scalar assignments of masked operations" (#1...Benjamin Maxwell7-16/+1398
10 hoursInstCombine: Use SimplifyDemandedFPClass on fmul (#177490)Matt Arsenault21-83/+84
11 hours[MemorySSA] Relax clobbering checks for calls to consider writes only (#179721)CarolineConcatto2-1/+14
11 hours[SimplifyLibCalls] Directly canonicalize fminimum_num to intrinsic (#180555)Nikita Popov2-26/+10
11 hours[OCaml] Remove global_context (#180533)Nikita Popov16-36/+42
11 hours[SDAG] Implement missing legalization for `ISD::VECTOR_FIND_LAST_ACTIVE` (#18...Benjamin Maxwell5-18/+381
11 hours[VPlan] Simplify true && x -> x (#179426)Mel Chen3-9/+10
11 hours[AMDGPU] Add intrinsic exposing s_alloc_vgpr (#163951)Diana Picus8-2/+186
12 hours[RISCV] Enable select optimization by default (#178394)Pengcheng Wang5-17/+37
12 hours[AMDGPU] Non convergent instruction does not depend on EXEC. NFCI. (#179821)Stanislav Mekhanoshin1-0/+4
13 hours[NewPM] Port x86-global-base-reg (#180119)Kyungtak Woo8-109/+161
14 hours[RISCV] Remove redundant czero in multi-word comparisons (#180485)Craig Topper3-74/+66
15 hours[DebugInfo] Fix an assertion in DWARFTypePrinter (#178986)Peter Rong2-3284/+3408
16 hoursFix LLDB data formatter for llvm::Expected<T> with non-reference types (#179294)jeffreytan811-2/+15
17 hours[RISCV] Rename FeatureEnableSelectOptimize to TuneEnableSelectOptimize (#180496)Pengcheng Wang1-1/+1
17 hoursAMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)vangthao953-181/+420
18 hoursLowerTypeTests: Optimize two-phase check used by llvm.cond.loop.Peter Collingbourne2-5/+65
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